util: do checkpoint aggregation more cleanly, fix last changeset.

1) Move alpha-specific code out of page_table.cc:serialize().
2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up.
3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN.
4) Fix the memory unserialize that I forgot somehow in the last changeset.
5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py.
Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA.

1 files changed, 5 insertions, 4 deletions

diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc
index 9d75d5fa1..1c83f64b2 100644
--- a/src/arch/alpha/process.cc
+++ b/src/arch/alpha/process.cc
@@ -175,21 +175,22 @@ AlphaLiveProcess::argsInit(int intSize, int pageSize)
 void
 AlphaLiveProcess::startup()
 {
-    if (checkpointRestored)
+    ThreadContext *tc = system->getThreadContext(contextIds[0]);
+    tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57);
+
+    if (checkpointRestored) {
         return;
+    }
 
     Process::startup();
 
     argsInit(MachineBytes, VMPageSize);
 
-    ThreadContext *tc = system->getThreadContext(contextIds[0]);
     tc->setIntReg(GlobalPointerReg, objFile->globalPointer());
     //Operate in user mode
     tc->setMiscRegNoEffect(IPR_ICM, 0x18);
     //No super page mapping
     tc->setMiscRegNoEffect(IPR_MCSR, 0);
-    //Set this to 0 for now, but it should be unique for each process
-    tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57);
 }
 
 AlphaISA::IntReg