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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
| commit | 32daf6fc3fd34af0023ae74c2a1f8dd597f87242 (patch) | |
| tree | 0868fb00a7546d90971bc18acd4f7b0bbce558c0 /src/arch/alpha/regfile.cc | |
| parent | 3e2cad8370d99f45ecf4d922d3ac8213e0d72644 (diff) | |
| download | gem5-32daf6fc3fd34af0023ae74c2a1f8dd597f87242.tar.xz | |
Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
Diffstat (limited to 'src/arch/alpha/regfile.cc')
| -rw-r--r-- | src/arch/alpha/regfile.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc index b3aa55b19..9009381b8 100644 --- a/src/arch/alpha/regfile.cc +++ b/src/arch/alpha/regfile.cc @@ -31,6 +31,7 @@ */ #include "arch/alpha/regfile.hh" +#include "arch/alpha/miscregfile.hh" #include "cpu/thread_context.hh" using namespace std; @@ -42,7 +43,6 @@ RegFile::serialize(EventManager *em, ostream &os) { intRegFile.serialize(os); floatRegFile.serialize(os); - miscRegFile.serialize(os); SERIALIZE_SCALAR(pc); SERIALIZE_SCALAR(npc); #if FULL_SYSTEM @@ -55,7 +55,6 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion) { intRegFile.unserialize(cp, section); floatRegFile.unserialize(cp, section); - miscRegFile.unserialize(cp, section); UNSERIALIZE_SCALAR(pc); UNSERIALIZE_SCALAR(npc); #if FULL_SYSTEM |