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authorGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:21 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:21 -0700
commit6ebce9d65ad5b06decedaab0ce39e0899bcd4d83 (patch)
treead46d12f54357f0f82d2673ac15e4e1f0aa331c8 /src/arch/alpha/regfile.cc
parentfaa6ebebe1121170778d005b384a21ce6da10308 (diff)
downloadgem5-6ebce9d65ad5b06decedaab0ce39e0899bcd4d83.tar.xz
Alpha: Phase out Alpha's intregfile.hh and intregfile.cc.
Diffstat (limited to 'src/arch/alpha/regfile.cc')
-rw-r--r--src/arch/alpha/regfile.cc14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc
index 993c91387..9a9ac41a7 100644
--- a/src/arch/alpha/regfile.cc
+++ b/src/arch/alpha/regfile.cc
@@ -38,6 +38,20 @@ using namespace std;
namespace AlphaISA {
+#if FULL_SYSTEM
+const int reg_redir[NumIntRegs] = {
+ /* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
+ /* 8 */ 32, 33, 34, 35, 36, 37, 38, 15,
+ /* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
+ /* 24 */ 24, 39, 26, 27, 28, 29, 30, 31 };
+#else
+const int reg_redir[NumIntRegs] = {
+ /* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
+ /* 8 */ 8, 9, 10, 11, 12, 13, 14, 15,
+ /* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
+ /* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 };
+#endif
+
void
RegFile::serialize(EventManager *em, ostream &os)
{