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author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
commit | d080581db1f9ee4e1e6d07d2b01c13c67908a391 (patch) | |
tree | cc484b289fa5a30c4631f9faa1d8b456bffeebfc /src/arch/alpha/regfile.cc | |
parent | 7a7c4c5fca83a8d47c7e71c9c080a882ebe204a9 (diff) | |
parent | 639cb0a42d953ee32bc7e96b0cdfa96cd40e9fc1 (diff) | |
download | gem5-d080581db1f9ee4e1e6d07d2b01c13c67908a391.tar.xz |
Merge ARM into the head. ARM will compile but may not actually work.
Diffstat (limited to 'src/arch/alpha/regfile.cc')
-rw-r--r-- | src/arch/alpha/regfile.cc | 103 |
1 files changed, 52 insertions, 51 deletions
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc index 2653310d7..b3aa55b19 100644 --- a/src/arch/alpha/regfile.cc +++ b/src/arch/alpha/regfile.cc @@ -33,67 +33,68 @@ #include "arch/alpha/regfile.hh" #include "cpu/thread_context.hh" -namespace AlphaISA +using namespace std; + +namespace AlphaISA { + +void +RegFile::serialize(EventManager *em, ostream &os) { - void - RegFile::serialize(std::ostream &os) - { - intRegFile.serialize(os); - floatRegFile.serialize(os); - miscRegFile.serialize(os); - SERIALIZE_SCALAR(pc); - SERIALIZE_SCALAR(npc); + intRegFile.serialize(os); + floatRegFile.serialize(os); + miscRegFile.serialize(os); + SERIALIZE_SCALAR(pc); + SERIALIZE_SCALAR(npc); #if FULL_SYSTEM - SERIALIZE_SCALAR(intrflag); + SERIALIZE_SCALAR(intrflag); #endif - } +} - void - RegFile::unserialize(Checkpoint *cp, const std::string §ion) - { - intRegFile.unserialize(cp, section); - floatRegFile.unserialize(cp, section); - miscRegFile.unserialize(cp, section); - UNSERIALIZE_SCALAR(pc); - UNSERIALIZE_SCALAR(npc); +void +RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion) +{ + intRegFile.unserialize(cp, section); + floatRegFile.unserialize(cp, section); + miscRegFile.unserialize(cp, section); + UNSERIALIZE_SCALAR(pc); + UNSERIALIZE_SCALAR(npc); #if FULL_SYSTEM - UNSERIALIZE_SCALAR(intrflag); + UNSERIALIZE_SCALAR(intrflag); #endif - } +} - void - copyRegs(ThreadContext *src, ThreadContext *dest) - { - // First loop through the integer registers. - for (int i = 0; i < NumIntRegs; ++i) { - dest->setIntReg(i, src->readIntReg(i)); - } +void +copyRegs(ThreadContext *src, ThreadContext *dest) +{ + // First loop through the integer registers. + for (int i = 0; i < NumIntRegs; ++i) + dest->setIntReg(i, src->readIntReg(i)); - // Then loop through the floating point registers. - for (int i = 0; i < TheISA::NumFloatRegs; ++i) { - dest->setFloatRegBits(i, src->readFloatRegBits(i)); - } + // Then loop through the floating point registers. + for (int i = 0; i < NumFloatRegs; ++i) + dest->setFloatRegBits(i, src->readFloatRegBits(i)); - // Copy misc. registers - copyMiscRegs(src, dest); + // Copy misc. registers + copyMiscRegs(src, dest); - // Lastly copy PC/NPC - dest->setPC(src->readPC()); - dest->setNextPC(src->readNextPC()); - } + // Lastly copy PC/NPC + dest->setPC(src->readPC()); + dest->setNextPC(src->readNextPC()); +} - void - copyMiscRegs(ThreadContext *src, ThreadContext *dest) - { - dest->setMiscRegNoEffect(AlphaISA::MISCREG_FPCR, - src->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR)); - dest->setMiscRegNoEffect(AlphaISA::MISCREG_UNIQ, - src->readMiscRegNoEffect(AlphaISA::MISCREG_UNIQ)); - dest->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, - src->readMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG)); - dest->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR, - src->readMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR)); +void +copyMiscRegs(ThreadContext *src, ThreadContext *dest) +{ + dest->setMiscRegNoEffect(MISCREG_FPCR, + src->readMiscRegNoEffect(MISCREG_FPCR)); + dest->setMiscRegNoEffect(MISCREG_UNIQ, + src->readMiscRegNoEffect(MISCREG_UNIQ)); + dest->setMiscRegNoEffect(MISCREG_LOCKFLAG, + src->readMiscRegNoEffect(MISCREG_LOCKFLAG)); + dest->setMiscRegNoEffect(MISCREG_LOCKADDR, + src->readMiscRegNoEffect(MISCREG_LOCKADDR)); - copyIprs(src, dest); - } + copyIprs(src, dest); } + +} // namespace AlphaISA |