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authorNathan Binkert <nate@binkert.org>2008-09-27 21:03:47 -0700
committerNathan Binkert <nate@binkert.org>2008-09-27 21:03:47 -0700
commit82f5723c7a8b245e1f60190a78b7fe383c2caf9b (patch)
tree8e3e2266820d903d9ef313a02fc10967711919a1 /src/arch/alpha/regfile.cc
parent8ea5176b7f4eac09d152dd63d0ba07962be9c865 (diff)
downloadgem5-82f5723c7a8b245e1f60190a78b7fe383c2caf9b.tar.xz
alpha: Clean up namespace usage.
Diffstat (limited to 'src/arch/alpha/regfile.cc')
-rw-r--r--src/arch/alpha/regfile.cc18
1 files changed, 9 insertions, 9 deletions
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc
index 3faa189ca..e617b00ae 100644
--- a/src/arch/alpha/regfile.cc
+++ b/src/arch/alpha/regfile.cc
@@ -70,7 +70,7 @@ namespace AlphaISA
}
// Then loop through the floating point registers.
- for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) {
+ for (int i = 0; i < NumFloatRegs; ++i) {
dest->setFloatRegBits(i, src->readFloatRegBits(i));
}
@@ -85,14 +85,14 @@ namespace AlphaISA
void
copyMiscRegs(ThreadContext *src, ThreadContext *dest)
{
- dest->setMiscRegNoEffect(AlphaISA::MISCREG_FPCR,
- src->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR));
- dest->setMiscRegNoEffect(AlphaISA::MISCREG_UNIQ,
- src->readMiscRegNoEffect(AlphaISA::MISCREG_UNIQ));
- dest->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG,
- src->readMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG));
- dest->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR,
- src->readMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR));
+ dest->setMiscRegNoEffect(MISCREG_FPCR,
+ src->readMiscRegNoEffect(MISCREG_FPCR));
+ dest->setMiscRegNoEffect(MISCREG_UNIQ,
+ src->readMiscRegNoEffect(MISCREG_UNIQ));
+ dest->setMiscRegNoEffect(MISCREG_LOCKFLAG,
+ src->readMiscRegNoEffect(MISCREG_LOCKFLAG));
+ dest->setMiscRegNoEffect(MISCREG_LOCKADDR,
+ src->readMiscRegNoEffect(MISCREG_LOCKADDR));
copyIprs(src, dest);
}