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authorGabe Black <gblack@eecs.umich.edu>2006-11-01 16:44:45 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-11-01 16:44:45 -0500
commit2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0 (patch)
tree736bc7ea34184fb103fd836e67672521193602a7 /src/arch/alpha/regfile.hh
parentf3ba6d20f6070c30418866e627e2418f39b433dd (diff)
downloadgem5-2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0.tar.xz
Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults
--HG-- extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
Diffstat (limited to 'src/arch/alpha/regfile.hh')
-rw-r--r--src/arch/alpha/regfile.hh43
1 files changed, 19 insertions, 24 deletions
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index 8980fcb40..e806adbcb 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -122,17 +122,16 @@ namespace AlphaISA
MiscReg readReg(int misc_reg);
- MiscReg readRegWithEffect(int misc_reg, Fault &fault,
- ThreadContext *tc);
+ MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc);
//These functions should be removed once the simplescalar cpu model
//has been replaced.
int getInstAsid();
int getDataAsid();
- Fault setReg(int misc_reg, const MiscReg &val);
+ void setReg(int misc_reg, const MiscReg &val);
- Fault setRegWithEffect(int misc_reg, const MiscReg &val,
+ void setRegWithEffect(int misc_reg, const MiscReg &val,
ThreadContext *tc);
void clear()
@@ -153,9 +152,9 @@ namespace AlphaISA
InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
private:
- InternalProcReg readIpr(int idx, Fault &fault, ThreadContext *tc);
+ InternalProcReg readIpr(int idx, ThreadContext *tc);
- Fault setIpr(int idx, InternalProcReg val, ThreadContext *tc);
+ void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
#endif
friend class RegFile;
};
@@ -225,22 +224,20 @@ namespace AlphaISA
return miscRegFile.readReg(miscReg);
}
- MiscReg readMiscRegWithEffect(int miscReg,
- Fault &fault, ThreadContext *tc)
+ MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc)
{
- fault = NoFault;
- return miscRegFile.readRegWithEffect(miscReg, fault, tc);
+ return miscRegFile.readRegWithEffect(miscReg, tc);
}
- Fault setMiscReg(int miscReg, const MiscReg &val)
+ void setMiscReg(int miscReg, const MiscReg &val)
{
- return miscRegFile.setReg(miscReg, val);
+ miscRegFile.setReg(miscReg, val);
}
- Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
+ void setMiscRegWithEffect(int miscReg, const MiscReg &val,
ThreadContext * tc)
{
- return miscRegFile.setRegWithEffect(miscReg, val, tc);
+ miscRegFile.setRegWithEffect(miscReg, val, tc);
}
FloatReg readFloatReg(int floatReg)
@@ -263,26 +260,24 @@ namespace AlphaISA
return readFloatRegBits(floatReg);
}
- Fault setFloatReg(int floatReg, const FloatReg &val)
+ void setFloatReg(int floatReg, const FloatReg &val)
{
floatRegFile.d[floatReg] = val;
- return NoFault;
}
- Fault setFloatReg(int floatReg, const FloatReg &val, int width)
+ void setFloatReg(int floatReg, const FloatReg &val, int width)
{
- return setFloatReg(floatReg, val);
+ setFloatReg(floatReg, val);
}
- Fault setFloatRegBits(int floatReg, const FloatRegBits &val)
+ void setFloatRegBits(int floatReg, const FloatRegBits &val)
{
floatRegFile.q[floatReg] = val;
- return NoFault;
}
- Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
+ void setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
{
- return setFloatRegBits(floatReg, val);
+ setFloatRegBits(floatReg, val);
}
IntReg readIntReg(int intReg)
@@ -290,9 +285,9 @@ namespace AlphaISA
return intRegFile.readReg(intReg);
}
- Fault setIntReg(int intReg, const IntReg &val)
+ void setIntReg(int intReg, const IntReg &val)
{
- return intRegFile.setReg(intReg, val);
+ intRegFile.setReg(intReg, val);
}
void serialize(std::ostream &os);