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authorKevin Lim <ktlim@umich.edu>2006-06-07 14:46:18 -0400
committerKevin Lim <ktlim@umich.edu>2006-06-07 14:46:18 -0400
commit3e191b14776c7a2c967e80c24331b27a50b8df77 (patch)
tree45d452290a4407448e2d355ba020fe1148f242e4 /src/arch/alpha/regfile.hh
parenteb0e416998ce2546c768d2b9d9d8bf3a387a87be (diff)
downloadgem5-3e191b14776c7a2c967e80c24331b27a50b8df77.tar.xz
Clear misc regs at startup.
src/arch/alpha/regfile.hh: Define clear functions on the individual reg files. src/cpu/o3/regfile.hh: Be sure to clear the misc reg file at startup. --HG-- extra : convert_revision : 41e640887f0cf15d778c59a4dcd544d46899b527
Diffstat (limited to 'src/arch/alpha/regfile.hh')
-rw-r--r--src/arch/alpha/regfile.hh16
1 files changed, 13 insertions, 3 deletions
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index ed410fddb..1025412cd 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -62,6 +62,8 @@ namespace AlphaISA
void unserialize(Checkpoint *cp, const std::string &section);
+ void clear()
+ { bzero(regs, sizeof(regs)); }
};
class FloatRegFile
@@ -77,6 +79,8 @@ namespace AlphaISA
void unserialize(Checkpoint *cp, const std::string &section);
+ void clear()
+ { bzero(d, sizeof(d)); }
};
class MiscRegFile {
@@ -102,6 +106,12 @@ namespace AlphaISA
Fault setRegWithEffect(int misc_reg, const MiscReg &val,
ThreadContext *tc);
+ void clear()
+ {
+ fpcr = uniq = 0;
+ lock_flag = 0;
+ lock_addr = 0;
+ }
#if FULL_SYSTEM
protected:
typedef uint64_t InternalProcReg;
@@ -171,9 +181,9 @@ namespace AlphaISA
void clear()
{
- bzero(&intRegFile, sizeof(intRegFile));
- bzero(&floatRegFile, sizeof(floatRegFile));
- bzero(&miscRegFile, sizeof(miscRegFile));
+ intRegFile.clear();
+ floatRegFile.clear();
+ miscRegFile.clear();
}
MiscReg readMiscReg(int miscReg)