Registers: Add an ISA object which replaces the MiscRegFile.

This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.

1 files changed, 0 insertions, 50 deletions

diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index cbd3657f7..59b76efd5 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -93,23 +93,10 @@ class RegFile {
   protected:
     IntRegFile intRegFile;          // (signed) integer register file
     FloatRegFile floatRegFile;      // floating point register file
-    MiscRegFile miscRegFile;        // control register file
 
   public:
 #if FULL_SYSTEM
     int intrflag;                   // interrupt flag
-
-    int
-    instAsid()
-    {
-        return miscRegFile.getInstAsid();
-    }
-
-    int
-    dataAsid()
-    {
-        return miscRegFile.getDataAsid();
-    }
 #endif // FULL_SYSTEM
 
     void
@@ -117,31 +104,6 @@ class RegFile {
     {
         intRegFile.clear();
         floatRegFile.clear();
-        miscRegFile.clear();
-    }
-
-    MiscReg
-    readMiscRegNoEffect(int miscReg)
-    {
-        return miscRegFile.readRegNoEffect(miscReg);
-    }
-
-    MiscReg
-    readMiscReg(int miscReg, ThreadContext *tc)
-    {
-        return miscRegFile.readReg(miscReg, tc);
-    }
-
-    void
-    setMiscRegNoEffect(int miscReg, const MiscReg &val)
-    {
-        miscRegFile.setRegNoEffect(miscReg, val);
-    }
-
-    void
-    setMiscReg(int miscReg, const MiscReg &val, ThreadContext *tc)
-    {
-        miscRegFile.setReg(miscReg, val, tc);
     }
 
     FloatReg
@@ -209,18 +171,6 @@ class RegFile {
         const std::string &section);
 };
 
-static inline int
-flattenIntIndex(ThreadContext * tc, int reg)
-{
-    return reg;
-}
-
-static inline int
-flattenFloatIndex(ThreadContext * tc, int reg)
-{
-    return reg;
-}
-
 void copyRegs(ThreadContext *src, ThreadContext *dest);
 
 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);