style: Make a style pass over the whole arch/alpha directory.

1 files changed, 151 insertions, 122 deletions

diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index 0c1f07bdd..c9fa8a91b 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -45,161 +45,190 @@
 class Checkpoint;
 class ThreadContext;
 
-namespace AlphaISA
-{
-
-    class RegFile {
+namespace AlphaISA {
 
-      protected:
-        Addr pc;                        // program counter
-        Addr npc;                       // next-cycle program counter
-        Addr nnpc;
+class RegFile {
+  protected:
+    Addr pc;   // program counter
+    Addr npc;  // next-cycle program counter
+    Addr nnpc; // next next-cycle program counter
 
-      public:
-        Addr readPC()
-        {
-            return pc;
-        }
-
-        void setPC(Addr val)
-        {
-            pc = val;
-        }
+  public:
+    Addr
+    readPC()
+    {
+        return pc;
+    }
 
-        Addr readNextPC()
-        {
-            return npc;
-        }
+    void
+    setPC(Addr val)
+    {
+        pc = val;
+    }
 
-        void setNextPC(Addr val)
-        {
-            npc = val;
-        }
+    Addr
+    readNextPC()
+    {
+        return npc;
+    }
 
-        Addr readNextNPC()
-        {
-            return npc + sizeof(MachInst);
-        }
+    void
+    setNextPC(Addr val)
+    {
+        npc = val;
+    }
 
-        void setNextNPC(Addr val)
-        { }
+    Addr
+    readNextNPC()
+    {
+        return npc + sizeof(MachInst);
+    }
 
-      protected:
-        IntRegFile intRegFile;          // (signed) integer register file
-        FloatRegFile floatRegFile;      // floating point register file
-        MiscRegFile miscRegFile;        // control register file
+    void
+    setNextNPC(Addr val)
+    { }
 
-      public:
+  protected:
+    IntRegFile intRegFile;          // (signed) integer register file
+    FloatRegFile floatRegFile;      // floating point register file
+    MiscRegFile miscRegFile;        // control register file
 
+  public:
 #if FULL_SYSTEM
-        int intrflag;                   // interrupt flag
-        inline int instAsid()
-        { return miscRegFile.getInstAsid(); }
-        inline int dataAsid()
-        { return miscRegFile.getDataAsid(); }
-#endif // FULL_SYSTEM
+    int intrflag;                   // interrupt flag
 
-        void clear()
-        {
-            intRegFile.clear();
-            floatRegFile.clear();
-            miscRegFile.clear();
-        }
-
-        MiscReg readMiscRegNoEffect(int miscReg)
-        {
-            return miscRegFile.readRegNoEffect(miscReg);
-        }
+    int
+    instAsid()
+    {
+        return miscRegFile.getInstAsid();
+    }
 
-        MiscReg readMiscReg(int miscReg, ThreadContext *tc)
-        {
-            return miscRegFile.readReg(miscReg, tc);
-        }
+    int
+    dataAsid()
+    {
+        return miscRegFile.getDataAsid();
+    }
+#endif // FULL_SYSTEM
 
-        void setMiscRegNoEffect(int miscReg, const MiscReg &val)
-        {
-            miscRegFile.setRegNoEffect(miscReg, val);
-        }
+    void
+    clear()
+    {
+        intRegFile.clear();
+        floatRegFile.clear();
+        miscRegFile.clear();
+    }
 
-        void setMiscReg(int miscReg, const MiscReg &val,
-                ThreadContext * tc)
-        {
-            miscRegFile.setReg(miscReg, val, tc);
-        }
+    MiscReg
+    readMiscRegNoEffect(int miscReg)
+    {
+        return miscRegFile.readRegNoEffect(miscReg);
+    }
 
-        FloatReg readFloatReg(int floatReg)
-        {
-            return floatRegFile.d[floatReg];
-        }
+    MiscReg
+    readMiscReg(int miscReg, ThreadContext *tc)
+    {
+        return miscRegFile.readReg(miscReg, tc);
+    }
 
-        FloatReg readFloatReg(int floatReg, int width)
-        {
-            return readFloatReg(floatReg);
-        }
+    void
+    setMiscRegNoEffect(int miscReg, const MiscReg &val)
+    {
+        miscRegFile.setRegNoEffect(miscReg, val);
+    }
 
-        FloatRegBits readFloatRegBits(int floatReg)
-        {
-            return floatRegFile.q[floatReg];
-        }
+    void
+    setMiscReg(int miscReg, const MiscReg &val, ThreadContext *tc)
+    {
+        miscRegFile.setReg(miscReg, val, tc);
+    }
 
-        FloatRegBits readFloatRegBits(int floatReg, int width)
-        {
-            return readFloatRegBits(floatReg);
-        }
+    FloatReg
+    readFloatReg(int floatReg)
+    {
+        return floatRegFile.d[floatReg];
+    }
 
-        void setFloatReg(int floatReg, const FloatReg &val)
-        {
-            floatRegFile.d[floatReg] = val;
-        }
+    FloatReg
+    readFloatReg(int floatReg, int width)
+    {
+        return readFloatReg(floatReg);
+    }
 
-        void setFloatReg(int floatReg, const FloatReg &val, int width)
-        {
-            setFloatReg(floatReg, val);
-        }
+    FloatRegBits
+    readFloatRegBits(int floatReg)
+    {
+        return floatRegFile.q[floatReg];
+    }
 
-        void setFloatRegBits(int floatReg, const FloatRegBits &val)
-        {
-            floatRegFile.q[floatReg] = val;
-        }
+    FloatRegBits
+    readFloatRegBits(int floatReg, int width)
+    {
+        return readFloatRegBits(floatReg);
+    }
 
-        void setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
-        {
-            setFloatRegBits(floatReg, val);
-        }
+    void
+    setFloatReg(int floatReg, const FloatReg &val)
+    {
+        floatRegFile.d[floatReg] = val;
+    }
 
-        IntReg readIntReg(int intReg)
-        {
-            return intRegFile.readReg(intReg);
-        }
+    void
+    setFloatReg(int floatReg, const FloatReg &val, int width)
+    {
+        setFloatReg(floatReg, val);
+    }
 
-        void setIntReg(int intReg, const IntReg &val)
-        {
-            intRegFile.setReg(intReg, val);
-        }
+    void
+    setFloatRegBits(int floatReg, const FloatRegBits &val)
+    {
+        floatRegFile.q[floatReg] = val;
+    }
 
-        void serialize(std::ostream &os);
-        void unserialize(Checkpoint *cp, const std::string &section);
+    void
+    setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
+    {
+        setFloatRegBits(floatReg, val);
+    }
 
-        void changeContext(RegContextParam param, RegContextVal val)
-        {
-            //This would be an alternative place to call/implement
-            //the swapPALShadow function
-        }
-    };
+    IntReg
+    readIntReg(int intReg)
+    {
+        return intRegFile.readReg(intReg);
+    }
 
-    static inline int flattenIntIndex(ThreadContext * tc, int reg)
+    void
+    setIntReg(int intReg, const IntReg &val)
     {
-        return reg;
+        intRegFile.setReg(intReg, val);
     }
 
-    static inline int flattenFloatIndex(ThreadContext * tc, int reg)
+    void serialize(std::ostream &os);
+    void unserialize(Checkpoint *cp, const std::string &section);
+
+    void
+    changeContext(RegContextParam param, RegContextVal val)
     {
-        return reg;
+        //This would be an alternative place to call/implement
+        //the swapPALShadow function
     }
+};
+
+static inline int
+flattenIntIndex(ThreadContext * tc, int reg)
+{
+    return reg;
+}
+
+static inline int
+flattenFloatIndex(ThreadContext * tc, int reg)
+{
+    return reg;
+}
+
+void copyRegs(ThreadContext *src, ThreadContext *dest);
 
-    void copyRegs(ThreadContext *src, ThreadContext *dest);
+void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 
-    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 } // namespace AlphaISA
 
-#endif
+#endif // __ARCH_ALPHA_REGFILE_HH__