arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700

1 files changed, 1 insertions, 11 deletions

diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 3fd774cf7..03bbd8aaf 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -33,6 +33,7 @@
 
 #include "arch/alpha/generated/max_inst_regs.hh"
 #include "arch/alpha/ipr.hh"
+#include "arch/generic/types.hh"
 #include "base/types.hh"
 
 namespace AlphaISA {
@@ -43,7 +44,6 @@ using AlphaISAInst::MaxInstDestRegs;
 // Locked read/write flags are can't be detected by the ISA parser
 const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
 
-typedef uint8_t RegIndex;
 typedef uint64_t IntReg;
 
 // floating point register file entry type
@@ -100,16 +100,6 @@ const int NumMiscRegs = NUM_MISCREGS;
 const int TotalNumRegs =
     NumIntRegs + NumFloatRegs + NumMiscRegs;
 
-// These enumerate all the registers for dependence tracking.
-enum DependenceTags {
-    // 0..31 are the integer regs 0..31
-    // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Reg_Base)
-    FP_Reg_Base = NumIntRegs,
-    CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
-    Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0
-    Max_Reg_Index = Misc_Reg_Base + NumMiscRegs + NumInternalProcRegs
-};
-
 } // namespace AlphaISA
 
 #endif // __ARCH_ALPHA_REGFILE_HH__