diff options
| author | Nathan Binkert <binkertn@umich.edu> | 2007-02-21 16:42:16 -0800 |
|---|---|---|
| committer | Nathan Binkert <binkertn@umich.edu> | 2007-02-21 16:42:16 -0800 |
| commit | 06ae2d04455d39acb1db642952e56b6a0359cf22 (patch) | |
| tree | d5ce7af9d3dbdeb3180af720547e53dc7df9bf99 /src/arch/alpha/tlb.cc | |
| parent | 2a67f2b08cb2d478c3b425d778a75bb2ce46a813 (diff) | |
| download | gem5-06ae2d04455d39acb1db642952e56b6a0359cf22.tar.xz | |
Fix compile issues on gcc 4.1.x related to namespaces.
This basically involves moving the builder code outside of any
namespace. While we're at it, move a few braces outside of
a couple #if/#else/#endif blocks so it's easier to match up
the braces.
--HG--
extra : convert_revision : a7834532aadc63b0e0ff988dd5745049e02e6312
Diffstat (limited to 'src/arch/alpha/tlb.cc')
| -rw-r--r-- | src/arch/alpha/tlb.cc | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index c21bf94f5..1e0155138 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -46,8 +46,7 @@ using namespace std; using namespace EV5; -namespace AlphaISA -{ +namespace AlphaISA { /////////////////////////////////////////////////////////////////////// // // Alpha TLB @@ -116,10 +115,11 @@ TLB::checkCacheability(RequestPtr &req) #if ALPHA_TLASER - if (req->getPaddr() & PAddrUncachedBit39) { + if (req->getPaddr() & PAddrUncachedBit39) #else - if (req->getPaddr() & PAddrUncachedBit43) { + if (req->getPaddr() & PAddrUncachedBit43) #endif + { // IPR memory space not implemented if (PAddrIprSpace(req->getPaddr())) { return new UnimpFault("IPR memory space not implemented!"); @@ -313,10 +313,11 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) const // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 #if ALPHA_TLASER if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) && - VAddrSpaceEV5(req->getVaddr()) == 2) { + VAddrSpaceEV5(req->getVaddr()) == 2) #else - if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { + if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) #endif + { // only valid in kernel mode if (ICM_CM(tc->readMiscReg(IPR_ICM)) != mode_kernel) { @@ -487,10 +488,11 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const // Check for "superpage" mapping #if ALPHA_TLASER if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) && - VAddrSpaceEV5(req->getVaddr()) == 2) { + VAddrSpaceEV5(req->getVaddr()) == 2) #else - if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { + if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) #endif + { // only valid in kernel mode if (DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)) != @@ -592,6 +594,8 @@ TLB::index(bool advance) return *pte; } +/* end namespace AlphaISA */ } + DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB) BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) @@ -633,4 +637,3 @@ CREATE_SIM_OBJECT(DTB) } REGISTER_SIM_OBJECT("AlphaDTB", DTB) -} |