style: Make a style pass over the whole arch/alpha directory.

1 files changed, 33 insertions, 28 deletions

diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 5e231d4d8..9266b8337 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -45,16 +45,18 @@
 using namespace std;
 
 namespace AlphaISA {
+
 ///////////////////////////////////////////////////////////////////////
 //
 //  Alpha TLB
 //
+
 #ifdef DEBUG
 bool uncacheBit39 = false;
 bool uncacheBit40 = false;
 #endif
 
-#define MODE2MASK(X)                    (1 << (X))
+#define MODE2MASK(X) (1 << (X))
 
 TLB::TLB(const Params *p)
     : BaseTLB(p), size(p->size), nlu(0)
@@ -113,20 +115,20 @@ TLB::lookup(Addr vpn, uint8_t asn)
     return retval;
 }
 
-
 Fault
 TLB::checkCacheability(RequestPtr &req, bool itb)
 {
-// in Alpha, cacheability is controlled by upper-level bits of the
-// physical address
-
-/*
- * We support having the uncacheable bit in either bit 39 or bit 40.
- * The Turbolaser platform (and EV5) support having the bit in 39, but
- * Tsunami (which Linux assumes uses an EV6) generates accesses with
- * the bit in 40.  So we must check for both, but we have debug flags
- * to catch a weird case where both are used, which shouldn't happen.
- */
+    // in Alpha, cacheability is controlled by upper-level bits of the
+    // physical address
+
+    /*
+     * We support having the uncacheable bit in either bit 39 or bit
+     * 40.  The Turbolaser platform (and EV5) support having the bit
+     * in 39, but Tsunami (which Linux assumes uses an EV6) generates
+     * accesses with the bit in 40.  So we must check for both, but we
+     * have debug flags to catch a weird case where both are used,
+     * which shouldn't happen.
+     */
 
 
 #if ALPHA_TLASER
@@ -143,7 +145,8 @@ TLB::checkCacheability(RequestPtr &req, bool itb)
             req->setFlags(req->getFlags() | UNCACHEABLE);
 
 #if !ALPHA_TLASER
-            // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
+            // Clear bits 42:35 of the physical address (10-2 in
+            // Tsunami manual)
             req->setPaddr(req->getPaddr() & PAddrUncachedMask);
 #endif
         }
@@ -221,7 +224,8 @@ TLB::flushProcesses()
         ++i;
 
         if (!entry->asma) {
-            DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, entry->tag, entry->ppn);
+            DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index,
+                    entry->tag, entry->ppn);
             entry->valid = false;
             lookupTable.erase(cur);
         }
@@ -284,7 +288,6 @@ TLB::unserialize(Checkpoint *cp, const string &section)
     }
 }
 
-
 ///////////////////////////////////////////////////////////////////////
 //
 //  Alpha ITB
@@ -313,12 +316,11 @@ ITB::regStats()
     accesses = hits + misses;
 }
 
-
 Fault
 ITB::translate(RequestPtr &req, ThreadContext *tc)
 {
     //If this is a pal pc, then set PHYSICAL
-    if(FULL_SYSTEM && PcPAL(req->getPC()))
+    if (FULL_SYSTEM && PcPAL(req->getPC()))
         req->setFlags(req->getFlags() | PHYSICAL);
 
     if (PcPAL(req->getPC())) {
@@ -403,7 +405,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
 //
 //  Alpha DTB
 //
- DTB::DTB(const Params *p)
+DTB::DTB(const Params *p)
      : TLB(p)
 {}
 
@@ -484,7 +486,6 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
     mode_type mode =
         (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
 
-
     /**
      * Check for alignment faults
      */
@@ -522,14 +523,15 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
         if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
 #endif
         {
-
             // only valid in kernel mode
             if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) !=
                 mode_kernel) {
                 if (write) { write_acv++; } else { read_acv++; }
                 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
                                   MM_STAT_ACV_MASK);
-                return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
+
+                return new DtbAcvFault(req->getVaddr(), req->getFlags(),
+                                       flags);
             }
 
             req->setPaddr(req->getVaddr() & PAddrImplMask);
@@ -575,25 +577,28 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
                     uint64_t flags = MM_STAT_WR_MASK |
                         MM_STAT_ACV_MASK |
                         (entry->fonw ? MM_STAT_FONW_MASK : 0);
-                    return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
+                    return new DtbPageFault(req->getVaddr(), req->getFlags(),
+                                            flags);
                 }
                 if (entry->fonw) {
                     write_acv++;
-                    uint64_t flags = MM_STAT_WR_MASK |
-                        MM_STAT_FONW_MASK;
-                    return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
+                    uint64_t flags = MM_STAT_WR_MASK | MM_STAT_FONW_MASK;
+                    return new DtbPageFault(req->getVaddr(), req->getFlags(),
+                                            flags);
                 }
             } else {
                 if (!(entry->xre & MODE2MASK(mode))) {
                     read_acv++;
                     uint64_t flags = MM_STAT_ACV_MASK |
                         (entry->fonr ? MM_STAT_FONR_MASK : 0);
-                    return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
+                    return new DtbAcvFault(req->getVaddr(), req->getFlags(),
+                                           flags);
                 }
                 if (entry->fonr) {
                     read_acv++;
                     uint64_t flags = MM_STAT_FONR_MASK;
-                    return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
+                    return new DtbPageFault(req->getVaddr(), req->getFlags(),
+                                            flags);
                 }
             }
         }
@@ -622,7 +627,7 @@ TLB::index(bool advance)
     return *entry;
 }
 
-} // namespace AlphaISA
+/* end namespace AlphaISA */ }
 
 AlphaISA::ITB *
 AlphaITBParams::create()