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authorSteve Reinhardt <steve.reinhardt@amd.com>2016-02-06 17:21:18 -0800
committerSteve Reinhardt <steve.reinhardt@amd.com>2016-02-06 17:21:18 -0800
commitdc8018a5c3482008232e6faaa2d96cf20aed7485 (patch)
treea972ac4544e227397595baf6eeb30e1854f480fc /src/arch/alpha/tlb.cc
parentc8c82f09a282832d919f7eb073a47be838e65b29 (diff)
downloadgem5-dc8018a5c3482008232e6faaa2d96cf20aed7485.tar.xz
style: remove trailing whitespace
Result of running 'hg m5style --skip-all --fix-white -a'.
Diffstat (limited to 'src/arch/alpha/tlb.cc')
-rw-r--r--src/arch/alpha/tlb.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 5f0ed85db..3360b34c5 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -230,9 +230,9 @@ TLB::checkCacheability(RequestPtr &req, bool itb)
req->setPaddr(req->getPaddr() & PAddrUncachedMask);
}
// We shouldn't be able to read from an uncachable address in Alpha as
- // we don't have a ROM and we don't want to try to fetch from a device
- // register as we destroy any data that is clear-on-read.
- if (req->isUncacheable() && itb)
+ // we don't have a ROM and we don't want to try to fetch from a device
+ // register as we destroy any data that is clear-on-read.
+ if (req->isUncacheable() && itb)
return std::make_shared<UnimpFault>(
"CPU trying to fetch from uncached I/O");