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author | Gabe Black <gblack@eecs.umich.edu> | 2008-02-26 23:38:51 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2008-02-26 23:38:51 -0500 |
commit | 8b4796a367ec21d294f7318343e5bb9d7e07a53e (patch) | |
tree | 584199359a9a7aa3c7d842164b677d1a1e94a1f1 /src/arch/alpha/tlb.hh | |
parent | 7bde0285e50e3903e38dd9e6fd59ea4a98f41079 (diff) | |
download | gem5-8b4796a367ec21d294f7318343e5bb9d7e07a53e.tar.xz |
TLB: Make a TLB base class and put a virtual demapPage function in it.
--HG--
extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
Diffstat (limited to 'src/arch/alpha/tlb.hh')
-rw-r--r-- | src/arch/alpha/tlb.hh | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh index 69a33f32d..e61ae5c6d 100644 --- a/src/arch/alpha/tlb.hh +++ b/src/arch/alpha/tlb.hh @@ -44,7 +44,7 @@ #include "params/AlphaDTB.hh" #include "params/AlphaITB.hh" #include "sim/faults.hh" -#include "sim/sim_object.hh" +#include "sim/tlb.hh" class ThreadContext; @@ -52,7 +52,7 @@ namespace AlphaISA { class TlbEntry; - class TLB : public SimObject + class TLB : public BaseTLB { protected: typedef std::multimap<Addr, int> PageTable; @@ -79,6 +79,12 @@ namespace AlphaISA void flushProcesses(); void flushAddr(Addr addr, uint8_t asn); + void demapPage(Addr vaddr, uint64_t asn) + { + assert(asn < (1 << 8)); + flushAddr(vaddr, asn); + } + // static helper functions... really EV5 VM traits static bool validVirtualAddress(Addr vaddr) { // unimplemented bits must be all 0 or all 1 |