diff options
author | Miles Kaufmann <milesck@eecs.umich.edu> | 2007-08-30 15:16:59 -0400 |
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committer | Miles Kaufmann <milesck@eecs.umich.edu> | 2007-08-30 15:16:59 -0400 |
commit | 54cc0053f0a6822e47a49771976af6daaabc24bb (patch) | |
tree | 72e6c7879de698347832e1e1475afbb9c1be2b70 /src/arch/alpha/tlb.hh | |
parent | 9cb49ab9e0ff8917d20fd7dc81be3ce5ecc81bd8 (diff) | |
download | gem5-54cc0053f0a6822e47a49771976af6daaabc24bb.tar.xz |
params: Deprecate old-style constructors; update most SimObject constructors.
SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses
The SimObject(const std::string &name) constructor was removed. Subclasses
that still rely on that behavior must call the parent initializer as
: SimObject(makeParams(name))
--HG--
extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
Diffstat (limited to 'src/arch/alpha/tlb.hh')
-rw-r--r-- | src/arch/alpha/tlb.hh | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh index 8df47dbec..69a33f32d 100644 --- a/src/arch/alpha/tlb.hh +++ b/src/arch/alpha/tlb.hh @@ -41,6 +41,8 @@ #include "arch/alpha/vtophys.hh" #include "base/statistics.hh" #include "mem/request.hh" +#include "params/AlphaDTB.hh" +#include "params/AlphaITB.hh" #include "sim/faults.hh" #include "sim/sim_object.hh" @@ -64,7 +66,8 @@ namespace AlphaISA TlbEntry *lookup(Addr vpn, uint8_t asn); public: - TLB(const std::string &name, int size); + typedef AlphaTLBParams Params; + TLB(const Params *p); virtual ~TLB(); int getsize() const { return size; } @@ -113,7 +116,8 @@ namespace AlphaISA mutable Stats::Formula accesses; public: - ITB(const std::string &name, int size); + typedef AlphaITBParams Params; + ITB(const Params *p); virtual void regStats(); Fault translate(RequestPtr &req, ThreadContext *tc); @@ -136,7 +140,8 @@ namespace AlphaISA Stats::Formula accesses; public: - DTB(const std::string &name, int size); + typedef AlphaDTBParams Params; + DTB(const Params *p); virtual void regStats(); Fault translate(RequestPtr &req, ThreadContext *tc, bool write); |