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| author | Andreas Sandberg <andreas@sandberg.pp.se> | 2013-06-03 13:55:41 +0200 |
|---|---|---|
| committer | Andreas Sandberg <andreas@sandberg.pp.se> | 2013-06-03 13:55:41 +0200 |
| commit | 7846f59d0dcb36c13e06a3ba8a4c461e646582b6 (patch) | |
| tree | 32b0ebd81cabb265409ad09e42285d2615354bdb /src/arch/alpha/tlb.hh | |
| parent | 63dae287035c9670c0622eefc9a19e0dc05c299f (diff) | |
| download | gem5-7846f59d0dcb36c13e06a3ba8a4c461e646582b6.tar.xz | |
arch: Create a method to finalize physical addresses
in the TLB
Some architectures (currently only x86) require some fixing-up of
physical addresses after a normal address translation. This is usually
to remap devices such as the APIC, but could be used for other memory
mapped devices as well. When running the CPU in a using hardware
virtualization, we still need to do these address fix-ups before
inserting the request into the memory system. This patch moves this
patch allows that code to be used by such CPUs without doing full
address translations.
Diffstat (limited to 'src/arch/alpha/tlb.hh')
| -rw-r--r-- | src/arch/alpha/tlb.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh index 4e56100c7..3300e5761 100644 --- a/src/arch/alpha/tlb.hh +++ b/src/arch/alpha/tlb.hh @@ -148,6 +148,7 @@ class TLB : public BaseTLB * translateFunctional stub function for future CheckerCPU support */ Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode); + Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; }; } // namespace AlphaISA |