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authorYasuko Eckert <yasuko.eckert@amd.com>2013-10-15 14:22:44 -0400
committerYasuko Eckert <yasuko.eckert@amd.com>2013-10-15 14:22:44 -0400
commit2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch)
tree040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/arch/alpha/utility.cc
parent552622184752dc798bc81f9b0b395db68aee9511 (diff)
downloadgem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz
cpu: add a condition-code register class
Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
Diffstat (limited to 'src/arch/alpha/utility.cc')
-rw-r--r--src/arch/alpha/utility.cc3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index 32fc0b141..2dfe00f96 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -71,6 +71,9 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
for (int i = 0; i < NumFloatRegs; ++i)
dest->setFloatRegBits(i, src->readFloatRegBits(i));
+ // Would need to add condition-code regs if implemented
+ assert(NumCCRegs == 0);
+
// Copy misc. registers
copyMiscRegs(src, dest);