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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-07 15:04:31 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-07 15:04:31 -0500 |
| commit | 689cab36c90b56b3c8a7cda16d758acdd89f9de1 (patch) | |
| tree | 2f0115320e0a6cfd13e5b054baa0ca13d5655519 /src/arch/alpha/utility.hh | |
| parent | 329db76e47c825d4ecbe0f5251dbcfaf2ec09516 (diff) | |
| download | gem5-689cab36c90b56b3c8a7cda16d758acdd89f9de1.tar.xz | |
*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
--HG--
extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
Diffstat (limited to 'src/arch/alpha/utility.hh')
| -rw-r--r-- | src/arch/alpha/utility.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index 9a06cc2a4..c8a50e8a2 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -45,7 +45,7 @@ namespace AlphaISA static inline bool inUserMode(ThreadContext *tc) { - return (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; + return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; } static inline ExtMachInst |