Make the predecoder an object with it's own switched header file. Start adding predecoding functionality to x86.

src/arch/SConscript:
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/cpu/base.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/static_inst.hh:
src/arch/alpha/predecoder.hh:
src/arch/mips/predecoder.hh:
src/arch/sparc/predecoder.hh:
    Make the predecoder an object with it's own switched header file.

--HG--
extra : convert_revision : 77206e29089130e86b97164c30022a062699ba86

1 files changed, 0 insertions, 15 deletions

diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index e4b8368a8..95d52c3fe 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -48,21 +48,6 @@ namespace AlphaISA
         return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
     }
 
-    enum PredecodeResult {
-        MoreBytes = 1,
-        ExtMIReady = 2
-    };
-
-    static inline unsigned int
-    predecode(ExtMachInst & ext_inst, Addr pc, MachInst inst, ThreadContext *) {
-        ext_inst = inst;
-#if FULL_SYSTEM
-        if (pc && 0x1)
-            ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
-#endif
-        return MoreBytes | ExtMIReady;
-    }
-
     inline bool isCallerSaveIntegerRegister(unsigned int reg) {
         panic("register classification not implemented");
         return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);