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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-03-13 16:13:21 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-03-13 16:13:21 +0000 |
| commit | ce18d900a17cdda2cc041b51c56e6c84fb155331 (patch) | |
| tree | d7be0cac19e550c93fc207e749ea80e1cf9a639e /src/arch/alpha/utility.hh | |
| parent | 8edc9d79cee3edd6d16a8254a0180aaa242974c7 (diff) | |
| download | gem5-ce18d900a17cdda2cc041b51c56e6c84fb155331.tar.xz | |
Replaced makeExtMI with predecode.
Removed the getOpcode function from StaticInst which only made sense for Alpha.
Started implementing the x86 predecoder.
--HG--
extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d
Diffstat (limited to 'src/arch/alpha/utility.hh')
| -rw-r--r-- | src/arch/alpha/utility.hh | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index c8a50e8a2..e4b8368a8 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -48,17 +48,19 @@ namespace AlphaISA return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; } - static inline ExtMachInst - makeExtMI(MachInst inst, Addr pc) { + enum PredecodeResult { + MoreBytes = 1, + ExtMIReady = 2 + }; + + static inline unsigned int + predecode(ExtMachInst & ext_inst, Addr pc, MachInst inst, ThreadContext *) { + ext_inst = inst; #if FULL_SYSTEM - ExtMachInst ext_inst = inst; if (pc && 0x1) - return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32); - else - return ext_inst; -#else - return ExtMachInst(inst); + ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32); #endif + return MoreBytes | ExtMIReady; } inline bool isCallerSaveIntegerRegister(unsigned int reg) { |