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| author | Sujay Phadke <electronicsguy123@gmail.com> | 2018-01-23 23:24:12 +0530 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2018-02-01 04:43:48 +0000 |
| commit | 257a67826291712202299957223c64af7a61ea98 (patch) | |
| tree | 5e57dd2fc3660ec73be57902b11b1581159e67b7 /src/arch/alpha | |
| parent | c872143864dcfee85c22db3904b4c05d0f1ddeae (diff) | |
| download | gem5-257a67826291712202299957223c64af7a61ea98.tar.xz | |
alpha: fix for no 'break' in the case statement
gem5 won't compile correctly since g++ will throw a warning (error)
that the next case statement below this one is reachable since there is
no 'break' statement.
Signed-off-by: Sujay Phadke
Change-Id: Icab646ee5abcfeb6ba3e690909042927b4003eba
Reviewed-on: https://gem5-review.googlesource.com/7521
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/alpha')
| -rw-r--r-- | src/arch/alpha/ev5.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 4d72104b1..ae8efa4e6 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -303,6 +303,7 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc) if (tc->getKernelStats()) tc->getKernelStats()->mode(Kernel::kernel, tc); } + M5_FALLTHROUGH; case IPR_ICM: // only write two mode bits - processor mode |