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authorGabe Black <gblack@eecs.umich.edu>2009-02-25 10:15:44 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-02-25 10:15:44 -0800
commit5605079b1f20bc7f6a4a80c8d1e4daabe7125270 (patch)
tree29dfa1685e3e257e3857ef7f9672778d43582440 /src/arch/alpha
parenta1aba01a02a8c1261120de83d8fbfd6624f0cb17 (diff)
downloadgem5-5605079b1f20bc7f6a4a80c8d1e4daabe7125270.tar.xz
ISA: Replace the translate functions in the TLBs with translateAtomic.
Diffstat (limited to 'src/arch/alpha')
-rw-r--r--src/arch/alpha/tlb.cc4
-rw-r--r--src/arch/alpha/tlb.hh4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index be02293d6..82d410987 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -317,7 +317,7 @@ ITB::regStats()
}
Fault
-ITB::translate(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
{
//If this is a pal pc, then set PHYSICAL
if (FULL_SYSTEM && PcPAL(req->getPC()))
@@ -479,7 +479,7 @@ DTB::regStats()
}
Fault
-DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
{
Addr pc = tc->readPC();
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 9267aa573..f5d2dbca9 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -131,7 +131,7 @@ class ITB : public TLB
ITB(const Params *p);
virtual void regStats();
- Fault translate(RequestPtr &req, ThreadContext *tc);
+ Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
};
class DTB : public TLB
@@ -155,7 +155,7 @@ class DTB : public TLB
DTB(const Params *p);
virtual void regStats();
- Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+ Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
};
} // namespace AlphaISA