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authorLisa Hsu <hsul@eecs.umich.edu>2008-11-02 21:56:57 -0500
committerLisa Hsu <hsul@eecs.umich.edu>2008-11-02 21:56:57 -0500
commitc55a467a06eaa59c47c52a2adddc266b8e545589 (patch)
treee86f0c75e6009285507cd2414b829c122bb0be1f /src/arch/alpha
parentf4bceb9760c93d3b5ff3c2606f7e460b42724670 (diff)
downloadgem5-c55a467a06eaa59c47c52a2adddc266b8e545589.tar.xz
make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch.
Diffstat (limited to 'src/arch/alpha')
-rw-r--r--src/arch/alpha/locked_mem.hh2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index f629d982a..6f4f5a748 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -87,7 +87,7 @@ handleLockedWrite(XC *xc, Request *req)
if (stCondFailures % 100000 == 0) {
warn("cpu %d: %d consecutive "
"store conditional failures\n",
- xc->readCpuId(), stCondFailures);
+ xc->cpuId(), stCondFailures);
}
// store conditional failed already, so don't issue it to mem