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authorKevin Lim <ktlim@umich.edu>2006-06-16 17:19:36 -0400
committerKevin Lim <ktlim@umich.edu>2006-06-16 17:19:36 -0400
commitdef9ea38b561676a89959882f92d3520a2e0224f (patch)
treeea4698e41533a762780b3bb201601c9347dc5f87 /src/arch/alpha
parentf4d0f92855a505448ddac4367d5d5c698d1e4282 (diff)
downloadgem5-def9ea38b561676a89959882f92d3520a2e0224f.tar.xz
Add in exec_context.hh, which is a file for documentation purposes only. It describes the ExecContext interface that the ISA uses to access CPU state. Also #ifdef Erik's old copy code from the decoder so ExecContext doesn't need his two specific copy functions.
src/arch/alpha/isa/decoder.isa: Surround Erik's old copy code with #ifdefs. This way the copy functions don't need to be included in the ExecContext (until somebody decides to add them back in). --HG-- extra : convert_revision : 508ca387757a32bb616e5b4b07af17787a76970e
Diffstat (limited to 'src/arch/alpha')
-rw-r--r--src/arch/alpha/isa/decoder.isa4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index d2908b27a..f449d2d69 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -47,9 +47,11 @@ decode OPCODE default Unknown::unknown() {
0x23: ldt({{ Fa = Mem.df; }});
0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED);
0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED);
+#ifdef USE_COPY
0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
{{ fault = xc->copySrcTranslate(EA); }},
inst_flags = [IsMemRef, IsLoad, IsCopy]);
+#endif
}
format LoadOrPrefetch {
@@ -69,9 +71,11 @@ decode OPCODE default Unknown::unknown() {
0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
0x27: stt({{ Mem.df = Fa; }});
+#ifdef USE_COPY
0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
{{ fault = xc->copy(EA); }},
inst_flags = [IsMemRef, IsStore, IsCopy]);
+#endif
}
format StoreCond {