arch, cpu: Add support for flattening misc register indexes.

With ARMv8 support the same misc register id  results in accessing different
registers depending on the current mode of the processor. This patch adds
the same orthogonality to the misc register file as the others (int, float, cc).
For all the othre ISAs this is currently a null-implementation.

Additionally, a system variable is added to all the ISA objects.

3 files changed, 15 insertions, 1 deletions

diff --git a/src/arch/alpha/AlphaISA.py b/src/arch/alpha/AlphaISA.py
index 64c9e4733..d85354704 100644
--- a/src/arch/alpha/AlphaISA.py
+++ b/src/arch/alpha/AlphaISA.py
@@ -35,9 +35,13 @@
 #
 # Authors: Andreas Sandberg
 
+from m5.params import *
+from m5.proxy import *
 from m5.SimObject import SimObject
 
 class AlphaISA(SimObject):
     type = 'AlphaISA'
     cxx_class = 'AlphaISA::ISA'
     cxx_header = "arch/alpha/isa.hh"
+
+    system = Param.System(Parent.any, "System this ISA object belongs to")
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index 9cfd840d9..95dfdedd6 100644
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -40,7 +40,7 @@ namespace AlphaISA
 {
 
 ISA::ISA(Params *p)
-    : SimObject(p)
+    : SimObject(p), system(p->system)
 {
     clear();
     initializeIprTable();
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index d30499066..35a26c108 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -39,6 +39,7 @@
 #include "arch/alpha/types.hh"
 #include "base/types.hh"
 #include "sim/sim_object.hh"
+#include "sim/system.hh"
 
 struct AlphaISAParams;
 class BaseCPU;
@@ -55,6 +56,9 @@ namespace AlphaISA
         typedef AlphaISAParams Params;
 
       protected:
+        // Parent system
+        System *system;
+
         uint64_t fpcr;       // floating point condition codes
         uint64_t uniq;       // process-unique register
         bool lock_flag;      // lock flag for LL/SC
@@ -110,6 +114,12 @@ namespace AlphaISA
             return reg;
         }
 
+        int
+        flattenMiscIndex(int reg)
+        {
+            return reg;
+        }
+
         const Params *params() const;
 
         ISA(Params *p);