Registers: Add an ISA object which replaces the MiscRegFile.

This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.

6 files changed, 184 insertions, 52 deletions

diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 069db2551..b10885e01 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -37,6 +37,7 @@ if env['TARGET_ISA'] == 'alpha':
     Source('floatregfile.cc')
     Source('intregfile.cc')
     Source('ipr.cc')
+    Source('isa.cc')
     Source('miscregfile.cc')
     Source('pagetable.cc')
     Source('regfile.cc')
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
new file mode 100644
index 000000000..ed452cfc6
--- /dev/null
+++ b/src/arch/alpha/isa.cc
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/alpha/isa.hh"
+#include "cpu/thread_context.hh"
+
+namespace AlphaISA
+{
+
+void
+ISA::clear()
+{
+    miscRegFile.clear();
+}
+
+MiscReg
+ISA::readMiscRegNoEffect(int miscReg)
+{
+    return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
+}
+
+MiscReg
+ISA::readMiscReg(int miscReg, ThreadContext *tc)
+{
+    return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
+}
+
+void
+ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+{
+    miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
+}
+
+void
+ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+{
+    miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
+}
+
+void
+ISA::serialize(std::ostream &os)
+{
+    miscRegFile.serialize(os);
+}
+
+void
+ISA::unserialize(Checkpoint *cp, const std::string &section)
+{
+    miscRegFile.unserialize(cp, section);
+}
+
+}
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
new file mode 100644
index 000000000..4c19659ab
--- /dev/null
+++ b/src/arch/alpha/isa.hh
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_ALPHA_ISA_HH__
+#define __ARCH_ALPHA_ISA_HH__
+
+#include "arch/alpha/miscregfile.hh"
+#include "arch/alpha/types.hh"
+
+class Checkpoint;
+class EventManager;
+
+namespace AlphaISA
+{
+    class ISA
+    {
+      protected:
+        MiscRegFile miscRegFile;
+
+      public:
+
+        void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
+        {
+            miscRegFile.expandForMultithreading(num_threads, num_vpes);
+        }
+
+        void reset(std::string core_name, ThreadID num_threads,
+                unsigned num_vpes, BaseCPU *_cpu)
+        {
+            miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
+        }
+
+        int instAsid()
+        {
+            return miscRegFile.getInstAsid();
+        }
+
+        int dataAsid()
+        {
+            return miscRegFile.getDataAsid();
+        }
+
+        void clear();
+
+        MiscReg readMiscRegNoEffect(int miscReg);
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+
+        void setMiscRegNoEffect(int miscReg, const MiscReg val);
+        void setMiscReg(int miscReg, const MiscReg val,
+                ThreadContext *tc);
+
+        int
+        flattenIntIndex(int reg)
+        {
+            return reg;
+        }
+
+        int
+        flattenFloatIndex(int reg)
+        {
+            return reg;
+        }
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
+
+        ISA()
+        {
+            clear();
+        }
+    };
+}
+
+#endif
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index aea44976c..d2b37590a 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -55,6 +55,7 @@ output header {{
 output decoder {{
 #include <cmath>
 
+#include "arch/alpha/miscregfile.hh"
 #include "base/cprintf.hh"
 #include "base/fenv.hh"
 #include "base/loader/symtab.hh"
@@ -71,6 +72,7 @@ output exec {{
 #include "base/cp_annotate.hh"
 #include "sim/pseudo_inst.hh"
 #include "arch/alpha/ipr.hh"
+#include "arch/alpha/miscregfile.hh"
 #include "base/fenv.hh"
 #include "config/ss_compatible_fp.hh"
 #include "cpu/base.hh"
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc
index b3aa55b19..9009381b8 100644
--- a/src/arch/alpha/regfile.cc
+++ b/src/arch/alpha/regfile.cc
@@ -31,6 +31,7 @@
  */
 
 #include "arch/alpha/regfile.hh"
+#include "arch/alpha/miscregfile.hh"
 #include "cpu/thread_context.hh"
 
 using namespace std;
@@ -42,7 +43,6 @@ RegFile::serialize(EventManager *em, ostream &os)
 {
     intRegFile.serialize(os);
     floatRegFile.serialize(os);
-    miscRegFile.serialize(os);
     SERIALIZE_SCALAR(pc);
     SERIALIZE_SCALAR(npc);
 #if FULL_SYSTEM
@@ -55,7 +55,6 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 {
     intRegFile.unserialize(cp, section);
     floatRegFile.unserialize(cp, section);
-    miscRegFile.unserialize(cp, section);
     UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
 #if FULL_SYSTEM
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index cbd3657f7..59b76efd5 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -93,23 +93,10 @@ class RegFile {
   protected:
     IntRegFile intRegFile;          // (signed) integer register file
     FloatRegFile floatRegFile;      // floating point register file
-    MiscRegFile miscRegFile;        // control register file
 
   public:
 #if FULL_SYSTEM
     int intrflag;                   // interrupt flag
-
-    int
-    instAsid()
-    {
-        return miscRegFile.getInstAsid();
-    }
-
-    int
-    dataAsid()
-    {
-        return miscRegFile.getDataAsid();
-    }
 #endif // FULL_SYSTEM
 
     void
@@ -117,31 +104,6 @@ class RegFile {
     {
         intRegFile.clear();
         floatRegFile.clear();
-        miscRegFile.clear();
-    }
-
-    MiscReg
-    readMiscRegNoEffect(int miscReg)
-    {
-        return miscRegFile.readRegNoEffect(miscReg);
-    }
-
-    MiscReg
-    readMiscReg(int miscReg, ThreadContext *tc)
-    {
-        return miscRegFile.readReg(miscReg, tc);
-    }
-
-    void
-    setMiscRegNoEffect(int miscReg, const MiscReg &val)
-    {
-        miscRegFile.setRegNoEffect(miscReg, val);
-    }
-
-    void
-    setMiscReg(int miscReg, const MiscReg &val, ThreadContext *tc)
-    {
-        miscRegFile.setReg(miscReg, val, tc);
     }
 
     FloatReg
@@ -209,18 +171,6 @@ class RegFile {
         const std::string &section);
 };
 
-static inline int
-flattenIntIndex(ThreadContext * tc, int reg)
-{
-    return reg;
-}
-
-static inline int
-flattenFloatIndex(ThreadContext * tc, int reg)
-{
-    return reg;
-}
-
 void copyRegs(ThreadContext *src, ThreadContext *dest);
 
 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);