Registers: Add a registers.hh file as an ISA switched header.

This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.

--HG--
rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh
rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh
rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh
rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh
rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh

10 files changed, 149 insertions, 193 deletions

diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 2780af104..06f30149d 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -38,7 +38,6 @@ if env['TARGET_ISA'] == 'alpha':
     Source('isa.cc')
     Source('miscregfile.cc')
     Source('pagetable.cc')
-    Source('regfile.cc')
     Source('regredir.cc')
     Source('remote_gdb.cc')
     Source('tlb.cc')
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index 8157ef7ec..66c240ef3 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -34,8 +34,6 @@
 
 namespace LittleEndianGuest {}
 
-#include "arch/alpha/ipr.hh"
-#include "arch/alpha/max_inst_regs.hh"
 #include "arch/alpha/types.hh"
 #include "base/types.hh"
 #include "config/full_system.hh"
@@ -45,16 +43,6 @@ class StaticInstPtr;
 namespace AlphaISA {
 
 using namespace LittleEndianGuest;
-using AlphaISAInst::MaxInstSrcRegs;
-using AlphaISAInst::MaxInstDestRegs;
-
-// These enumerate all the registers for dependence tracking.
-enum DependenceTags {
-    // 0..31 are the integer regs 0..31
-    // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
-    FP_Base_DepTag = 40,
-    Ctrl_Base_DepTag = 72
-};
 
 StaticInstPtr decodeInst(ExtMachInst);
 
@@ -128,21 +116,6 @@ enum mode_type
 // Constants Related to the number of registers
 
 enum {
-    // semantically meaningful register indices
-    ZeroReg = 31,     // architecturally meaningful
-    // the rest of these depend on the ABI
-    StackPointerReg = 30,
-    GlobalPointerReg = 29,
-    ProcedureValueReg = 27,
-    ReturnAddressReg = 26,
-    ReturnValueReg = 0,
-    FramePointerReg = 15,
-
-    SyscallNumReg = 0,
-    FirstArgumentReg = 16,
-    SyscallPseudoReturnReg = 20,
-    SyscallSuccessReg = 19,
-
     LogVMPageSize = 13,       // 8K bytes
     VMPageSize = (1 << LogVMPageSize),
 
diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh
index b231ea855..bcf61db15 100644
--- a/src/arch/alpha/miscregfile.hh
+++ b/src/arch/alpha/miscregfile.hh
@@ -34,7 +34,7 @@
 
 #include <iosfwd>
 
-#include "arch/alpha/ipr.hh"
+#include "arch/alpha/registers.hh"
 #include "arch/alpha/types.hh"
 #include "base/types.hh"
 #include "sim/serialize.hh"
@@ -45,15 +45,6 @@ class BaseCPU;
 
 namespace AlphaISA {
 
-enum MiscRegIndex
-{
-    MISCREG_FPCR = NumInternalProcRegs,
-    MISCREG_UNIQ,
-    MISCREG_LOCKFLAG,
-    MISCREG_LOCKADDR,
-    MISCREG_INTR
-};
-
 class MiscRegFile
 {
   public:
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc
deleted file mode 100644
index 0ddb9da8f..000000000
--- a/src/arch/alpha/regfile.cc
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- *          Gabe Black
- *          Kevin Lim
- */
-
-#include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/regfile.hh"
-#include "arch/alpha/miscregfile.hh"
-#include "cpu/thread_context.hh"
-
-using namespace std;
-
-namespace AlphaISA {
-
-void
-copyRegs(ThreadContext *src, ThreadContext *dest)
-{
-    // First loop through the integer registers.
-    for (int i = 0; i < NumIntRegs; ++i)
-        dest->setIntReg(i, src->readIntReg(i));
-
-    // Then loop through the floating point registers.
-    for (int i = 0; i < NumFloatRegs; ++i)
-        dest->setFloatRegBits(i, src->readFloatRegBits(i));
-
-    // Copy misc. registers
-    copyMiscRegs(src, dest);
-
-    // Lastly copy PC/NPC
-    dest->setPC(src->readPC());
-    dest->setNextPC(src->readNextPC());
-}
-
-void
-copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-    dest->setMiscRegNoEffect(MISCREG_FPCR,
-        src->readMiscRegNoEffect(MISCREG_FPCR));
-    dest->setMiscRegNoEffect(MISCREG_UNIQ,
-        src->readMiscRegNoEffect(MISCREG_UNIQ));
-    dest->setMiscRegNoEffect(MISCREG_LOCKFLAG,
-        src->readMiscRegNoEffect(MISCREG_LOCKFLAG));
-    dest->setMiscRegNoEffect(MISCREG_LOCKADDR,
-        src->readMiscRegNoEffect(MISCREG_LOCKADDR));
-
-    copyIprs(src, dest);
-}
-
-} // namespace AlphaISA
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
deleted file mode 100644
index c5fa981a6..000000000
--- a/src/arch/alpha/regfile.hh
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#ifndef __ARCH_ALPHA_REGFILE_HH__
-#define __ARCH_ALPHA_REGFILE_HH__
-
-#include "arch/alpha/ipr.hh"
-
-class ThreadContext;
-
-namespace AlphaISA {
-
-    const int NumIntArchRegs = 32;
-    const int NumPALShadowRegs = 8;
-    const int NumFloatArchRegs = 32;
-    // @todo: Figure out what this number really should be.
-    const int NumMiscArchRegs = 77;
-
-    const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
-    const int NumFloatRegs = NumFloatArchRegs;
-    const int NumMiscRegs = NumMiscArchRegs;
-
-    const int TotalNumRegs =
-        NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs;
-
-    const int TotalDataRegs = NumIntRegs + NumFloatRegs;
-
-
-void copyRegs(ThreadContext *src, ThreadContext *dest);
-
-void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_REGFILE_HH__
diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
new file mode 100644
index 000000000..ec36ff751
--- /dev/null
+++ b/src/arch/alpha/registers.hh
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_ALPHA_REGISTERS_HH__
+#define __ARCH_ALPHA_REGISTERS_HH__
+
+#include "arch/alpha/ipr.hh"
+#include "arch/alpha/max_inst_regs.hh"
+#include "base/types.hh"
+
+namespace AlphaISA {
+
+using AlphaISAInst::MaxInstSrcRegs;
+using AlphaISAInst::MaxInstDestRegs;
+
+typedef uint8_t RegIndex;
+typedef uint64_t IntReg;
+
+// floating point register file entry type
+typedef double FloatReg;
+typedef uint64_t FloatRegBits;
+
+// control register file contents
+typedef uint64_t MiscReg;
+
+union AnyReg
+{
+    IntReg  intreg;
+    FloatReg   fpreg;
+    MiscReg ctrlreg;
+};
+
+enum MiscRegIndex
+{
+    MISCREG_FPCR = NumInternalProcRegs,
+    MISCREG_UNIQ,
+    MISCREG_LOCKFLAG,
+    MISCREG_LOCKADDR,
+    MISCREG_INTR
+};
+
+// semantically meaningful register indices
+const RegIndex ZeroReg = 31;     // architecturally meaningful
+// the rest of these depend on the ABI
+const RegIndex StackPointerReg = 30;
+const RegIndex GlobalPointerReg = 29;
+const RegIndex ProcedureValueReg = 27;
+const RegIndex ReturnAddressReg = 26;
+const RegIndex ReturnValueReg = 0;
+const RegIndex FramePointerReg = 15;
+
+const RegIndex SyscallNumReg = 0;
+const RegIndex FirstArgumentReg = 16;
+const RegIndex SyscallPseudoReturnReg = 20;
+const RegIndex SyscallSuccessReg = 19;
+
+const int NumIntArchRegs = 32;
+const int NumPALShadowRegs = 8;
+const int NumFloatArchRegs = 32;
+// @todo: Figure out what this number really should be.
+const int NumMiscArchRegs = 77;
+
+const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
+const int NumFloatRegs = NumFloatArchRegs;
+const int NumMiscRegs = NumMiscArchRegs;
+
+const int TotalNumRegs =
+    NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs;
+
+const int TotalDataRegs = NumIntRegs + NumFloatRegs;
+
+// These enumerate all the registers for dependence tracking.
+enum DependenceTags {
+    // 0..31 are the integer regs 0..31
+    // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
+    FP_Base_DepTag = 40,
+    Ctrl_Base_DepTag = 72
+};
+
+} // namespace AlphaISA
+
+#endif // __ARCH_ALPHA_REGFILE_HH__
diff --git a/src/arch/alpha/regredir.hh b/src/arch/alpha/regredir.hh
index ac50ec482..6e12be41f 100644
--- a/src/arch/alpha/regredir.hh
+++ b/src/arch/alpha/regredir.hh
@@ -31,7 +31,7 @@
 #ifndef __ARCH_ALPHA_REGREDIR_HH__
 #define __ARCH_ALPHA_REGREDIR_HH__
 
-#include "arch/alpha/regfile.hh"
+#include "arch/alpha/registers.hh"
 
 namespace AlphaISA {
 
diff --git a/src/arch/alpha/types.hh b/src/arch/alpha/types.hh
index d670784c4..0d285c3b2 100644
--- a/src/arch/alpha/types.hh
+++ b/src/arch/alpha/types.hh
@@ -38,25 +38,9 @@ namespace AlphaISA {
 
 typedef uint32_t MachInst;
 typedef uint64_t ExtMachInst;
-typedef uint8_t  RegIndex;
 
-typedef uint64_t IntReg;
 typedef uint64_t LargestRead;
 
-// floating point register file entry type
-typedef double FloatReg;
-typedef uint64_t FloatRegBits;
-
-// control register file contents
-typedef uint64_t MiscReg;
-
-union AnyReg
-{
-    IntReg  intreg;
-    FloatReg   fpreg;
-    MiscReg ctrlreg;
-};
-
 enum annotes
 {
     ANNOTE_NONE = 0,
diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index 763da0d4f..c336a4fb3 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -61,5 +61,39 @@ getArgument(ThreadContext *tc, int number, bool fp)
 #endif
 }
 
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+    // First loop through the integer registers.
+    for (int i = 0; i < NumIntRegs; ++i)
+        dest->setIntReg(i, src->readIntReg(i));
+
+    // Then loop through the floating point registers.
+    for (int i = 0; i < NumFloatRegs; ++i)
+        dest->setFloatRegBits(i, src->readFloatRegBits(i));
+
+    // Copy misc. registers
+    copyMiscRegs(src, dest);
+
+    // Lastly copy PC/NPC
+    dest->setPC(src->readPC());
+    dest->setNextPC(src->readNextPC());
+}
+
+void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+    dest->setMiscRegNoEffect(MISCREG_FPCR,
+        src->readMiscRegNoEffect(MISCREG_FPCR));
+    dest->setMiscRegNoEffect(MISCREG_UNIQ,
+        src->readMiscRegNoEffect(MISCREG_UNIQ));
+    dest->setMiscRegNoEffect(MISCREG_LOCKFLAG,
+        src->readMiscRegNoEffect(MISCREG_LOCKFLAG));
+    dest->setMiscRegNoEffect(MISCREG_LOCKADDR,
+        src->readMiscRegNoEffect(MISCREG_LOCKADDR));
+
+    copyIprs(src, dest);
+}
+
 } // namespace AlphaISA
 
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index 71ee4aceb..de4261418 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -159,6 +159,10 @@ template <class TC>
 void processInterrupts(TC *tc);
 #endif
 
+void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
 } // namespace AlphaISA
 
 #endif // __ARCH_ALPHA_UTILITY_HH__