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author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-16 11:35:40 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-16 11:35:40 -0500 |
commit | 9d0ca61b7e357ca5e83f97f8cb8f4f1037cc3eb5 (patch) | |
tree | 50e7a435de1e0f5638eba9b1b030e79daaf1aee0 /src/arch/alpha | |
parent | 4da37bcd1bc2c42ce5f297a58b4b4bffa4e8cd4f (diff) | |
parent | f4f00c5ae98c069f79a8b56ed93284daf7532c7e (diff) | |
download | gem5-9d0ca61b7e357ca5e83f97f8cb8f4f1037cc3eb5.tar.xz |
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem
src/arch/isa_parser.py:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
src/cpu/o3/iew_impl.hh:
Hand Merge
--HG--
extra : convert_revision : ae1b25cde85ab8ec275a09d554acd372887d4d47
Diffstat (limited to 'src/arch/alpha')
-rw-r--r-- | src/arch/alpha/regfile.hh | 5 | ||||
-rw-r--r-- | src/arch/alpha/syscallreturn.hh | 45 |
2 files changed, 13 insertions, 37 deletions
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index ff5830822..c73c32bad 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -189,6 +189,11 @@ namespace AlphaISA } }; + static inline int flattenIntIndex(ThreadContext * tc, int reg) + { + return reg; + } + void copyRegs(ThreadContext *src, ThreadContext *dest); void copyMiscRegs(ThreadContext *src, ThreadContext *dest); diff --git a/src/arch/alpha/syscallreturn.hh b/src/arch/alpha/syscallreturn.hh index 803c3b7da..47b4ac8c7 100644 --- a/src/arch/alpha/syscallreturn.hh +++ b/src/arch/alpha/syscallreturn.hh @@ -32,54 +32,25 @@ #ifndef __ARCH_ALPHA_SYSCALLRETURN_HH__ #define __ARCH_ALPHA_SYSCALLRETURN_HH__ -class SyscallReturn { - public: - template <class T> - SyscallReturn(T v, bool s) - { - retval = (uint64_t)v; - success = s; - } - - template <class T> - SyscallReturn(T v) - { - success = (v >= 0); - retval = (uint64_t)v; - } - - ~SyscallReturn() {} - - SyscallReturn& operator=(const SyscallReturn& s) { - retval = s.retval; - success = s.success; - return *this; - } - - bool successful() { return success; } - uint64_t value() { return retval; } - - - private: - uint64_t retval; - bool success; -}; +#include "cpu/thread_context.hh" +#include "sim/syscallreturn.hh" namespace AlphaISA { - static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs) + static inline void setSyscallReturn(SyscallReturn return_value, + ThreadContext * tc) { // check for error condition. Alpha syscall convention is to // indicate success/failure in reg a3 (r19) and put the // return value itself in the standard return value reg (v0). if (return_value.successful()) { // no error - regs->setIntReg(SyscallSuccessReg, 0); - regs->setIntReg(ReturnValueReg, return_value.value()); + tc->setIntReg(SyscallSuccessReg, 0); + tc->setIntReg(ReturnValueReg, return_value.value()); } else { // got an error, return details - regs->setIntReg(SyscallSuccessReg, (IntReg)-1); - regs->setIntReg(ReturnValueReg, -return_value.value()); + tc->setIntReg(SyscallSuccessReg, (IntReg)-1); + tc->setIntReg(ReturnValueReg, -return_value.value()); } } } |