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| author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:15 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:15 -0400 |
| commit | 1c7e988272efead94d2cfbe3fd65ba454d3e1fc1 (patch) | |
| tree | 55affa4470c6cc8cdadc8da953895a0b3a163a24 /src/arch/alpha | |
| parent | f41df0ee08467711c613faadf9879052ab7196ed (diff) | |
| download | gem5-1c7e988272efead94d2cfbe3fd65ba454d3e1fc1.tar.xz | |
inorder-mem: skeleton support for prefetch/writehints
Diffstat (limited to 'src/arch/alpha')
| -rw-r--r-- | src/arch/alpha/isa/mem.isa | 18 | ||||
| -rw-r--r-- | src/arch/alpha/tlb.cc | 2 |
2 files changed, 8 insertions, 12 deletions
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa index b74eaacab..5bac4f758 100644 --- a/src/arch/alpha/isa/mem.isa +++ b/src/arch/alpha/isa/mem.isa @@ -164,14 +164,6 @@ def template MemAccSizeDeclare {{ int memAccSize(%(CPU_exec_context)s *xc); }}; -def template MiscMemAccSize {{ - int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc) - { - panic("Misc instruction does not support split access method!"); - return 0; - } -}}; - def template LoadStoreMemAccSize {{ int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc) { @@ -451,7 +443,8 @@ def template MiscInitiateAcc {{ Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - warn("Misc instruction does not support split access method!"); + warn("initiateAcc undefined: Misc instruction does not support split " + "access method!"); return NoFault; } }}; @@ -462,7 +455,8 @@ def template MiscCompleteAcc {{ %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - warn("Misc instruction does not support split access method!"); + warn("completeAcc undefined: Misc instruction does not support split " + "access method!"); return NoFault; } @@ -471,7 +465,9 @@ def template MiscCompleteAcc {{ def template MiscMemAccSize {{ int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc) { - panic("Misc instruction does not support split access method!"); + return (%(mem_acc_size)d / 8); + panic("memAccSize undefined: Misc instruction does not support split " + "access method!"); return 0; } }}; diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index d9e9dd342..b578741d9 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -452,7 +452,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) * Check for alignment faults */ if (req->getVaddr() & (req->getSize() - 1)) { - DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), + DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(), req->getSize()); uint64_t flags = write ? MM_STAT_WR_MASK : 0; return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); |