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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-26 18:57:16 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-26 18:57:16 -0500 |
| commit | 2939d7d061efc8444c06ac52f82c8aeaf0048aaf (patch) | |
| tree | 8c1d047e855505581ed7d9c6ba35c8077eb0fa6f /src/arch/alpha | |
| parent | 8561c8366c7c9afd7e6b52b6e2385b3c1dde95a9 (diff) | |
| download | gem5-2939d7d061efc8444c06ac52f82c8aeaf0048aaf.tar.xz | |
Make Sparc traceflag even more chatty
some fixes to fp instructions to use the single precision registers
if this is an fp op emit fp check code
add fpregs to m5legion struct
src/arch/sparc/floatregfile.cc:
Make Sparc traceflag even more chatty
src/arch/sparc/isa/base.isa:
add code to check if the fpu is enabled
src/arch/sparc/isa/decoder.isa:
some fixes to fp instructions to use the single precision registers
fix smul again
fix subc/subcc/subccc condition code setting
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/mem/util.isa:
if this is an fp op emit fp check code
src/cpu/exetrace.cc:
check fp regs as well as int regs
src/cpu/m5legion_interface.h:
add fpregs to m5legion struct
--HG--
extra : convert_revision : e7d26d10fb8ce88f96e3a51f84b48c3b3ad2f232
Diffstat (limited to 'src/arch/alpha')
0 files changed, 0 insertions, 0 deletions