Alpha: Pull the MiscRegFile fully into the ISA object.

12 files changed, 154 insertions, 330 deletions

diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 06f30149d..e3701d2a4 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -36,7 +36,6 @@ if env['TARGET_ISA'] == 'alpha':
     Source('faults.cc')
     Source('ipr.cc')
     Source('isa.cc')
-    Source('miscregfile.cc')
     Source('pagetable.cc')
     Source('regredir.cc')
     Source('remote_gdb.cc')
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index adbebb346..3bc0492b1 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -128,13 +128,13 @@ zeroRegisters(CPU *cpu)
 }
 
 int
-MiscRegFile::getInstAsid()
+ISA::getInstAsid()
 {
     return ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
 }
 
 int
-MiscRegFile::getDataAsid()
+ISA::getDataAsid()
 {
     return DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
 }
@@ -158,7 +158,7 @@ initIPRs(ThreadContext *tc, int cpuId)
 }
 
 MiscReg
-MiscRegFile::readIpr(int idx, ThreadContext *tc)
+ISA::readIpr(int idx, ThreadContext *tc)
 {
     uint64_t retval = 0;        // return value, default 0
 
@@ -270,7 +270,7 @@ int break_ipl = -1;
 #endif
 
 void
-MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
+ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
 {
     uint64_t old;
 
diff --git a/src/arch/alpha/ev5.hh b/src/arch/alpha/ev5.hh
index a135ac506..5abc7e57f 100644
--- a/src/arch/alpha/ev5.hh
+++ b/src/arch/alpha/ev5.hh
@@ -35,6 +35,8 @@
 
 #include "arch/alpha/isa_traits.hh"
 
+class ThreadContext;
+
 namespace AlphaISA {
 
 const uint64_t AsnMask = ULL(0xff);
@@ -106,6 +108,8 @@ inline int Ra(MachInst inst) { return inst >> 21 & 0x1f; }
 const Addr PalBase = 0x4000;
 const Addr PalMax = 0x10000;
 
+void copyIprs(ThreadContext *src, ThreadContext *dest);
+
 } // namespace AlphaISA
 
 #endif // __ARCH_ALPHA_EV5_HH__
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index ed452cfc6..eee391a0d 100644
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -29,51 +29,122 @@
  */
 
 #include "arch/alpha/isa.hh"
+#include "base/misc.hh"
 #include "cpu/thread_context.hh"
 
 namespace AlphaISA
 {
 
 void
-ISA::clear()
+ISA::serialize(std::ostream &os)
 {
-    miscRegFile.clear();
+    SERIALIZE_SCALAR(fpcr);
+    SERIALIZE_SCALAR(uniq);
+    SERIALIZE_SCALAR(lock_flag);
+    SERIALIZE_SCALAR(lock_addr);
+    SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
 }
 
-MiscReg
-ISA::readMiscRegNoEffect(int miscReg)
+void
+ISA::unserialize(Checkpoint *cp, const std::string &section)
 {
-    return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
+    UNSERIALIZE_SCALAR(fpcr);
+    UNSERIALIZE_SCALAR(uniq);
+    UNSERIALIZE_SCALAR(lock_flag);
+    UNSERIALIZE_SCALAR(lock_addr);
+    UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
 }
 
-MiscReg
-ISA::readMiscReg(int miscReg, ThreadContext *tc)
-{
-    return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
-}
 
-void
-ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+MiscReg
+ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
 {
-    miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
+    switch (misc_reg) {
+      case MISCREG_FPCR:
+        return fpcr;
+      case MISCREG_UNIQ:
+        return uniq;
+      case MISCREG_LOCKFLAG:
+        return lock_flag;
+      case MISCREG_LOCKADDR:
+        return lock_addr;
+      case MISCREG_INTR:
+        return intr_flag;
+      default:
+        assert(misc_reg < NumInternalProcRegs);
+        return ipr[misc_reg];
+    }
 }
 
-void
-ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+MiscReg
+ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
 {
-    miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
+    switch (misc_reg) {
+      case MISCREG_FPCR:
+        return fpcr;
+      case MISCREG_UNIQ:
+        return uniq;
+      case MISCREG_LOCKFLAG:
+        return lock_flag;
+      case MISCREG_LOCKADDR:
+        return lock_addr;
+      case MISCREG_INTR:
+        return intr_flag;
+      default:
+        return readIpr(misc_reg, tc);
+    }
 }
 
 void
-ISA::serialize(std::ostream &os)
+ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
 {
-    miscRegFile.serialize(os);
+    switch (misc_reg) {
+      case MISCREG_FPCR:
+        fpcr = val;
+        return;
+      case MISCREG_UNIQ:
+        uniq = val;
+        return;
+      case MISCREG_LOCKFLAG:
+        lock_flag = val;
+        return;
+      case MISCREG_LOCKADDR:
+        lock_addr = val;
+        return;
+      case MISCREG_INTR:
+        intr_flag = val;
+        return;
+      default:
+        assert(misc_reg < NumInternalProcRegs);
+        ipr[misc_reg] = val;
+        return;
+    }
 }
 
 void
-ISA::unserialize(Checkpoint *cp, const std::string &section)
+ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
+                ThreadID tid)
 {
-    miscRegFile.unserialize(cp, section);
+    switch (misc_reg) {
+      case MISCREG_FPCR:
+        fpcr = val;
+        return;
+      case MISCREG_UNIQ:
+        uniq = val;
+        return;
+      case MISCREG_LOCKFLAG:
+        lock_flag = val;
+        return;
+      case MISCREG_LOCKADDR:
+        lock_addr = val;
+        return;
+      case MISCREG_INTR:
+        intr_flag = val;
+        return;
+      default:
+        setIpr(misc_reg, val, tc);
+        return;
+    }
 }
 
 }
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 4c19659ab..dbd1c43a9 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -31,50 +31,73 @@
 #ifndef __ARCH_ALPHA_ISA_HH__
 #define __ARCH_ALPHA_ISA_HH__
 
-#include "arch/alpha/miscregfile.hh"
+#include <string>
+#include <iostream>
+
+#include "arch/alpha/registers.hh"
 #include "arch/alpha/types.hh"
+#include "base/types.hh"
 
+class BaseCPU;
 class Checkpoint;
 class EventManager;
+class ThreadContext;
 
 namespace AlphaISA
 {
     class ISA
     {
+      public:
+        typedef uint64_t InternalProcReg;
+
+      protected:
+        uint64_t fpcr;       // floating point condition codes
+        uint64_t uniq;       // process-unique register
+        bool lock_flag;      // lock flag for LL/SC
+        Addr lock_addr;      // lock address for LL/SC
+        int intr_flag;
+
+        InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
+
       protected:
-        MiscRegFile miscRegFile;
+        InternalProcReg readIpr(int idx, ThreadContext *tc);
+        void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
 
       public:
 
-        void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
-        {
-            miscRegFile.expandForMultithreading(num_threads, num_vpes);
-        }
+        // These functions should be removed once the simplescalar cpu
+        // model has been replaced.
+        int getInstAsid();
+        int getDataAsid();
 
-        void reset(std::string core_name, ThreadID num_threads,
-                unsigned num_vpes, BaseCPU *_cpu)
-        {
-            miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
-        }
+        MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
+        MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
 
-        int instAsid()
-        {
-            return miscRegFile.getInstAsid();
-        }
+        void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
+                                ThreadID tid = 0);
+        void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
+                        ThreadID tid = 0);
 
-        int dataAsid()
+        void
+        clear()
         {
-            return miscRegFile.getDataAsid();
+            fpcr = 0;
+            uniq = 0;
+            lock_flag = 0;
+            lock_addr = 0;
+            intr_flag = 0;
         }
 
-        void clear();
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
 
-        MiscReg readMiscRegNoEffect(int miscReg);
-        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+        void reset(std::string core_name, ThreadID num_threads,
+                   unsigned num_vpes, BaseCPU *_cpu)
+        { }
 
-        void setMiscRegNoEffect(int miscReg, const MiscReg val);
-        void setMiscReg(int miscReg, const MiscReg val,
-                ThreadContext *tc);
+
+        void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
+        { }
 
         int
         flattenIntIndex(int reg)
@@ -88,12 +111,10 @@ namespace AlphaISA
             return reg;
         }
 
-        void serialize(std::ostream &os);
-        void unserialize(Checkpoint *cp, const std::string &section);
-
         ISA()
         {
             clear();
+            initializeIprTable();
         }
     };
 }
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 2be325a08..2a0699354 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -55,7 +55,7 @@ output header {{
 output decoder {{
 #include <cmath>
 
-#include "arch/alpha/miscregfile.hh"
+#include "arch/alpha/registers.hh"
 #include "arch/alpha/regredir.hh"
 #include "base/cprintf.hh"
 #include "base/fenv.hh"
@@ -73,8 +73,7 @@ output exec {{
 #include "arch/alpha/regredir.hh"
 #include "base/cp_annotate.hh"
 #include "sim/pseudo_inst.hh"
-#include "arch/alpha/ipr.hh"
-#include "arch/alpha/miscregfile.hh"
+#include "arch/alpha/registers.hh"
 #include "base/fenv.hh"
 #include "config/ss_compatible_fp.hh"
 #include "cpu/base.hh"
diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index e8928ba08..86958e4c5 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -45,7 +45,7 @@
  * to do these manipulations based on the physical address.
  */
 
-#include "arch/alpha/miscregfile.hh"
+#include "arch/alpha/registers.hh"
 #include "base/misc.hh"
 #include "mem/request.hh"
 
diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc
deleted file mode 100644
index d52d900fd..000000000
--- a/src/arch/alpha/miscregfile.cc
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- *          Gabe Black
- *          Kevin Lim
- */
-
-#include <cassert>
-
-#include "arch/alpha/miscregfile.hh"
-#include "base/misc.hh"
-
-namespace AlphaISA {
-
-void
-MiscRegFile::serialize(std::ostream &os)
-{
-    SERIALIZE_SCALAR(fpcr);
-    SERIALIZE_SCALAR(uniq);
-    SERIALIZE_SCALAR(lock_flag);
-    SERIALIZE_SCALAR(lock_addr);
-    SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
-}
-
-void
-MiscRegFile::unserialize(Checkpoint *cp, const std::string &section)
-{
-    UNSERIALIZE_SCALAR(fpcr);
-    UNSERIALIZE_SCALAR(uniq);
-    UNSERIALIZE_SCALAR(lock_flag);
-    UNSERIALIZE_SCALAR(lock_addr);
-    UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
-}
-
-MiscRegFile::MiscRegFile(BaseCPU *_cpu)
-{
-    cpu = _cpu;
-    initializeIprTable();
-}
-
-
-MiscReg
-MiscRegFile::readRegNoEffect(int misc_reg, ThreadID tid)
-{
-    switch (misc_reg) {
-      case MISCREG_FPCR:
-        return fpcr;
-      case MISCREG_UNIQ:
-        return uniq;
-      case MISCREG_LOCKFLAG:
-        return lock_flag;
-      case MISCREG_LOCKADDR:
-        return lock_addr;
-      case MISCREG_INTR:
-        return intr_flag;
-      default:
-        assert(misc_reg < NumInternalProcRegs);
-        return ipr[misc_reg];
-    }
-}
-
-MiscReg
-MiscRegFile::readReg(int misc_reg, ThreadContext *tc, ThreadID tid)
-{
-    switch (misc_reg) {
-      case MISCREG_FPCR:
-        return fpcr;
-      case MISCREG_UNIQ:
-        return uniq;
-      case MISCREG_LOCKFLAG:
-        return lock_flag;
-      case MISCREG_LOCKADDR:
-        return lock_addr;
-      case MISCREG_INTR:
-        return intr_flag;
-      default:
-        return readIpr(misc_reg, tc);
-    }
-}
-
-void
-MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
-{
-    switch (misc_reg) {
-      case MISCREG_FPCR:
-        fpcr = val;
-        return;
-      case MISCREG_UNIQ:
-        uniq = val;
-        return;
-      case MISCREG_LOCKFLAG:
-        lock_flag = val;
-        return;
-      case MISCREG_LOCKADDR:
-        lock_addr = val;
-        return;
-      case MISCREG_INTR:
-        intr_flag = val;
-        return;
-      default:
-        assert(misc_reg < NumInternalProcRegs);
-        ipr[misc_reg] = val;
-        return;
-    }
-}
-
-void
-MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
-                    ThreadID tid)
-{
-    switch (misc_reg) {
-      case MISCREG_FPCR:
-        fpcr = val;
-        return;
-      case MISCREG_UNIQ:
-        uniq = val;
-        return;
-      case MISCREG_LOCKFLAG:
-        lock_flag = val;
-        return;
-      case MISCREG_LOCKADDR:
-        lock_addr = val;
-        return;
-      case MISCREG_INTR:
-        intr_flag = val;
-        return;
-      default:
-        setIpr(misc_reg, val, tc);
-        return;
-    }
-}
-
-} // namespace AlphaISA
diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh
deleted file mode 100644
index bcf61db15..000000000
--- a/src/arch/alpha/miscregfile.hh
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- *          Gabe Black
- */
-
-#ifndef __ARCH_ALPHA_MISCREGFILE_HH__
-#define __ARCH_ALPHA_MISCREGFILE_HH__
-
-#include <iosfwd>
-
-#include "arch/alpha/registers.hh"
-#include "arch/alpha/types.hh"
-#include "base/types.hh"
-#include "sim/serialize.hh"
-
-class Checkpoint;
-class ThreadContext;
-class BaseCPU;
-
-namespace AlphaISA {
-
-class MiscRegFile
-{
-  public:
-    typedef uint64_t InternalProcReg;
-
-  protected:
-    uint64_t fpcr;       // floating point condition codes
-    uint64_t uniq;       // process-unique register
-    bool lock_flag;      // lock flag for LL/SC
-    Addr lock_addr;      // lock address for LL/SC
-    int intr_flag;
-
-    InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
-
-    BaseCPU *cpu;
-
-  protected:
-    InternalProcReg readIpr(int idx, ThreadContext *tc);
-    void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
-
-  public:
-    MiscRegFile()
-    {
-        initializeIprTable();
-    }
-
-    MiscRegFile(BaseCPU *cpu);
-
-    // These functions should be removed once the simplescalar cpu
-    // model has been replaced.
-    int getInstAsid();
-    int getDataAsid();
-
-    MiscReg readRegNoEffect(int misc_reg, ThreadID tid = 0);
-    MiscReg readReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
-
-    void setRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0);
-    void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
-                ThreadID tid = 0);
-
-    void
-    clear()
-    {
-        fpcr = 0;
-        uniq = 0;
-        lock_flag = 0;
-        lock_addr = 0;
-        intr_flag = 0;
-    }
-
-    void serialize(std::ostream &os);
-    void unserialize(Checkpoint *cp, const std::string &section);
-
-    void reset(std::string core_name, ThreadID num_threads,
-               unsigned num_vpes, BaseCPU *_cpu)
-    { }
-
-
-    void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
-    { }
-
-
-};
-
-void copyIprs(ThreadContext *src, ThreadContext *dest);
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_MISCREGFILE_HH__
diff --git a/src/arch/alpha/mmaped_ipr.hh b/src/arch/alpha/mmaped_ipr.hh
index af2469ca7..99f8aeb06 100644
--- a/src/arch/alpha/mmaped_ipr.hh
+++ b/src/arch/alpha/mmaped_ipr.hh
@@ -37,8 +37,11 @@
  * ISA-specific helper functions for memory mapped IPR accesses.
  */
 
+#include "base/types.hh"
 #include "mem/packet.hh"
 
+class ThreadContext;
+
 namespace AlphaISA {
 
 inline Tick
diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index c336a4fb3..0d865e520 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -29,6 +29,7 @@
  *          Ali Saidi
  */
 
+#include "arch/alpha/ev5.hh"
 #include "arch/alpha/utility.hh"
 
 #if FULL_SYSTEM
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index de4261418..0b994d324 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -34,7 +34,7 @@
 
 #include "arch/alpha/types.hh"
 #include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/miscregfile.hh"
+#include "arch/alpha/registers.hh"
 #include "base/misc.hh"
 #include "config/full_system.hh"
 #include "cpu/thread_context.hh"