ISA: Get rid of old, unused utility functions cluttering up the ISAs.

2 files changed, 0 insertions, 116 deletions

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 609b45957..0db75df46 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -66,53 +66,6 @@ initCPU(ThreadContext *tc, int cpuId)
     delete reset;
 }
 
-
-template <class CPU>
-void
-processInterrupts(CPU *cpu)
-{
-    //Check if there are any outstanding interrupts
-    //Handle the interrupts
-    int ipl = 0;
-    int summary = 0;
-
-    if (cpu->readMiscRegNoEffect(IPR_ASTRR))
-        panic("asynchronous traps not implemented\n");
-
-    if (cpu->readMiscRegNoEffect(IPR_SIRR)) {
-        for (int i = INTLEVEL_SOFTWARE_MIN;
-             i < INTLEVEL_SOFTWARE_MAX; i++) {
-            if (cpu->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
-                // See table 4-19 of the 21164 hardware reference
-                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
-                summary |= (ULL(1) << i);
-            }
-        }
-    }
-
-    uint64_t interrupts = cpu->intr_status();
-
-    if (interrupts) {
-        for (int i = INTLEVEL_EXTERNAL_MIN;
-             i < INTLEVEL_EXTERNAL_MAX; i++) {
-            if (interrupts & (ULL(1) << i)) {
-                // See table 4-19 of the 21164 hardware reference
-                ipl = i;
-                summary |= (ULL(1) << i);
-            }
-        }
-    }
-
-    if (ipl && ipl > cpu->readMiscRegNoEffect(IPR_IPLR)) {
-        cpu->setMiscRegNoEffect(IPR_ISR, summary);
-        cpu->setMiscRegNoEffect(IPR_INTID, ipl);
-        cpu->trap(new InterruptFault);
-        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
-                cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
-    }
-
-}
-
 template <class CPU>
 void
 zeroRegisters(CPU *cpu)
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index 0b994d324..281fc4492 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -49,68 +49,6 @@ inUserMode(ThreadContext *tc)
     return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
 }
 
-inline bool
-isCallerSaveIntegerRegister(unsigned int reg)
-{
-    panic("register classification not implemented");
-    return (reg >= 1 && reg <= 8) || (reg >= 22 && reg <= 25) || reg == 27;
-}
-
-inline bool
-isCalleeSaveIntegerRegister(unsigned int reg)
-{
-    panic("register classification not implemented");
-    return reg >= 9 && reg <= 15;
-}
-
-inline bool
-isCallerSaveFloatRegister(unsigned int reg)
-{
-    panic("register classification not implemented");
-    return false;
-}
-
-inline bool
-isCalleeSaveFloatRegister(unsigned int reg)
-{
-    panic("register classification not implemented");
-    return false;
-}
-
-inline Addr
-alignAddress(const Addr &addr, unsigned int nbytes)
-{
-    return (addr & ~(nbytes - 1));
-}
-
-// Instruction address compression hooks
-inline Addr
-realPCToFetchPC(const Addr &addr)
-{
-    return addr;
-}
-
-inline Addr
-fetchPCToRealPC(const Addr &addr)
-{
-    return addr;
-}
-
-// the size of "fetched" instructions (not necessarily the size
-// of real instructions for PISA)
-inline size_t
-fetchInstSize()
-{
-    return sizeof(MachInst);
-}
-
-inline MachInst
-makeRegisterCopy(int dest, int src)
-{
-    panic("makeRegisterCopy not implemented");
-    return 0;
-}
-
 /**
  * Function to insure ISA semantics about 0 registers.
  * @param tc The thread context.
@@ -150,13 +88,6 @@ RoundPage(Addr addr)
 void initIPRs(ThreadContext *tc, int cpuId);
 #if FULL_SYSTEM
 void initCPU(ThreadContext *tc, int cpuId);
-
-/**
- * Function to check for and process any interrupts.
- * @param tc The thread context.
- */
-template <class TC>
-void processInterrupts(TC *tc);
 #endif
 
 void copyRegs(ThreadContext *src, ThreadContext *dest);