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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-20 17:18:35 -0400 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-20 17:18:35 -0400 |
| commit | e1403fc2af61c224c573c47c77a36f9b1b78e7df (patch) | |
| tree | 07647bb8697ac256d180bf8de35080eee2a63f3e /src/arch/alpha | |
| parent | 2b0438a11eb6a9640b06da91e8a300d0ac3ad81a (diff) | |
| download | gem5-e1403fc2af61c224c573c47c77a36f9b1b78e7df.tar.xz | |
alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate
activate(), suspend(), and halt() used on thread contexts had an optional
delay parameter. However this parameter was often ignored. Also, when used,
the delay was seemily arbitrarily set to 0 or 1 cycle (no other delays were
ever specified). This patch removes the delay parameter and 'Events'
associated with them across all ISAs and cores. Unused activate logic
is also removed.
Diffstat (limited to 'src/arch/alpha')
| -rw-r--r-- | src/arch/alpha/utility.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index 1cd19cc95..72643cb16 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -68,7 +68,7 @@ void zeroRegisters(TC *tc); // Alpha IPR register accessors inline bool PcPAL(Addr addr) { return addr & 0x3; } inline void startupCPU(ThreadContext *tc, int cpuId) -{ tc->activate(Cycles(0)); } +{ tc->activate(); } //////////////////////////////////////////////////////////////////////// // |