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authorKevin Lim <ktlim@umich.edu>2007-03-23 13:14:05 -0400
committerKevin Lim <ktlim@umich.edu>2007-03-23 13:14:05 -0400
commit2330adfa28ec39035beab8dae52873ecd0e28889 (patch)
treeeaefa5635426a0e1558bb25c15d664b9a6ce2887 /src/arch/alpha
parent941d3168d02347728181ddb02d486d2fafa14131 (diff)
downloadgem5-2330adfa28ec39035beab8dae52873ecd0e28889.tar.xz
Make hardware loads/stores serializing; they need to avoid certain out-of-order interactions in the 21264.
--HG-- extra : convert_revision : d83940af7d0e8efe891d574ac42c6d70d179e2b1
Diffstat (limited to 'src/arch/alpha')
-rw-r--r--src/arch/alpha/isa/decoder.isa10
1 files changed, 6 insertions, 4 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 6df47ef7a..03c8cc29e 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -719,8 +719,10 @@ decode OPCODE default Unknown::unknown() {
0: OpcdecFault::hw_st_quad();
1: decode HW_LDST_QUAD {
format HwLoad {
- 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
- 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
+ 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }},
+ L, IsSerializing, IsSerializeBefore);
+ 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }},
+ Q, IsSerializing, IsSerializeBefore);
}
}
}
@@ -731,9 +733,9 @@ decode OPCODE default Unknown::unknown() {
1: decode HW_LDST_COND {
0: decode HW_LDST_QUAD {
0: hw_st({{ EA = (Rb + disp) & ~3; }},
- {{ Mem.ul = Ra<31:0>; }}, L);
+ {{ Mem.ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
1: hw_st({{ EA = (Rb + disp) & ~7; }},
- {{ Mem.uq = Ra.uq; }}, Q);
+ {{ Mem.uq = Ra.uq; }}, Q, IsSerializing, IsSerializeBefore);
}
1: FailUnimpl::hw_st_cond();