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author | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
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committer | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
commit | 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch) | |
tree | 040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/arch/alpha | |
parent | 552622184752dc798bc81f9b0b395db68aee9511 (diff) | |
download | gem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz |
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
Diffstat (limited to 'src/arch/alpha')
-rw-r--r-- | src/arch/alpha/isa.hh | 7 | ||||
-rw-r--r-- | src/arch/alpha/registers.hh | 7 | ||||
-rw-r--r-- | src/arch/alpha/utility.cc | 3 |
3 files changed, 16 insertions, 1 deletions
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh index e2e2daba8..d30499066 100644 --- a/src/arch/alpha/isa.hh +++ b/src/arch/alpha/isa.hh @@ -103,6 +103,13 @@ namespace AlphaISA return reg; } + // dummy + int + flattenCCIndex(int reg) + { + return reg; + } + const Params *params() const; ISA(Params *p); diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh index 92ba22ee8..3fd774cf7 100644 --- a/src/arch/alpha/registers.hh +++ b/src/arch/alpha/registers.hh @@ -53,6 +53,9 @@ typedef uint64_t FloatRegBits; // control register file contents typedef uint64_t MiscReg; +// dummy typedef since we don't have CC regs +typedef uint8_t CCReg; + union AnyReg { IntReg intreg; @@ -91,6 +94,7 @@ const int NumFloatArchRegs = 32; const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; const int NumFloatRegs = NumFloatArchRegs; +const int NumCCRegs = 0; const int NumMiscRegs = NUM_MISCREGS; const int TotalNumRegs = @@ -101,7 +105,8 @@ enum DependenceTags { // 0..31 are the integer regs 0..31 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Reg_Base) FP_Reg_Base = NumIntRegs, - Misc_Reg_Base = FP_Reg_Base + NumFloatRegs, + CC_Reg_Base = FP_Reg_Base + NumFloatRegs, + Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0 Max_Reg_Index = Misc_Reg_Base + NumMiscRegs + NumInternalProcRegs }; diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc index 32fc0b141..2dfe00f96 100644 --- a/src/arch/alpha/utility.cc +++ b/src/arch/alpha/utility.cc @@ -71,6 +71,9 @@ copyRegs(ThreadContext *src, ThreadContext *dest) for (int i = 0; i < NumFloatRegs; ++i) dest->setFloatRegBits(i, src->readFloatRegBits(i)); + // Would need to add condition-code regs if implemented + assert(NumCCRegs == 0); + // Copy misc. registers copyMiscRegs(src, dest); |