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author | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2012-11-02 11:32:01 -0500 |
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committer | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2012-11-02 11:32:01 -0500 |
commit | c0ab52799ca4ebd0a51363cfedd0658e6d79b842 (patch) | |
tree | afdf65e4593c64bbc1d5b511aacbaf0fa4b558ad /src/arch/alpha | |
parent | 044a6525876efc61838dffa89ac52425d510b754 (diff) | |
download | gem5-c0ab52799ca4ebd0a51363cfedd0658e6d79b842.tar.xz |
sim: Include object header files in SWIG interfaces
When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.
This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
Diffstat (limited to 'src/arch/alpha')
-rw-r--r-- | src/arch/alpha/AlphaInterrupts.py | 1 | ||||
-rw-r--r-- | src/arch/alpha/AlphaSystem.py | 4 | ||||
-rw-r--r-- | src/arch/alpha/AlphaTLB.py | 1 |
3 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/alpha/AlphaInterrupts.py b/src/arch/alpha/AlphaInterrupts.py index ecfcf5c21..a75b11fc0 100644 --- a/src/arch/alpha/AlphaInterrupts.py +++ b/src/arch/alpha/AlphaInterrupts.py @@ -31,3 +31,4 @@ from m5.SimObject import SimObject class AlphaInterrupts(SimObject): type = 'AlphaInterrupts' cxx_class = 'AlphaISA::Interrupts' + cxx_header = "arch/alpha/interrupts.hh" diff --git a/src/arch/alpha/AlphaSystem.py b/src/arch/alpha/AlphaSystem.py index fcbe81edd..2486ec059 100644 --- a/src/arch/alpha/AlphaSystem.py +++ b/src/arch/alpha/AlphaSystem.py @@ -32,6 +32,7 @@ from System import System class AlphaSystem(System): type = 'AlphaSystem' + cxx_header = "arch/alpha/system.hh" console = Param.String("file that contains the console code") pal = Param.String("file that contains palcode") system_type = Param.UInt64("Type of system we are emulating") @@ -40,6 +41,7 @@ class AlphaSystem(System): class LinuxAlphaSystem(AlphaSystem): type = 'LinuxAlphaSystem' + cxx_header = "arch/alpha/linux/system.hh" system_type = 34 system_rev = 1 << 10 @@ -48,10 +50,12 @@ class LinuxAlphaSystem(AlphaSystem): class FreebsdAlphaSystem(AlphaSystem): type = 'FreebsdAlphaSystem' + cxx_header = "arch/alpha/freebsd/system.hh" system_type = 34 system_rev = 1 << 10 class Tru64AlphaSystem(AlphaSystem): type = 'Tru64AlphaSystem' + cxx_header = "arch/alpha/tru64/system.hh" system_type = 12 system_rev = 2<<1 diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py index 51f636ec2..8031c719f 100644 --- a/src/arch/alpha/AlphaTLB.py +++ b/src/arch/alpha/AlphaTLB.py @@ -34,6 +34,7 @@ from BaseTLB import BaseTLB class AlphaTLB(BaseTLB): type = 'AlphaTLB' cxx_class = 'AlphaISA::TLB' + cxx_header = "arch/alpha/tlb.hh" size = Param.Int("TLB size") class AlphaDTB(AlphaTLB): |