summaryrefslogtreecommitdiff
path: root/src/arch/alpha
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2013-08-19 03:52:29 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-08-19 03:52:29 -0400
commitf7d44590cb5455c2b70c2b26005bbbcdd771de18 (patch)
treeac05f01011e15e9daa8a8d8e078be703837c4f36 /src/arch/alpha
parent6211c24a969735ecc9c83fceb59386c7d636253d (diff)
downloadgem5-f7d44590cb5455c2b70c2b26005bbbcdd771de18.tar.xz
alpha: Check interrupts before quiesce
This patch adds a check to the quiesce operation to ensure that the CPU does not suspend itself when there are unmasked interrupts pending. Without this patch there are corner cases when the CPU gets an interrupt before the quiesce is executed and then never wakes up again.
Diffstat (limited to 'src/arch/alpha')
-rw-r--r--src/arch/alpha/isa/decoder.isa21
1 files changed, 20 insertions, 1 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 9785e217c..93863b50d 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -1,5 +1,17 @@
// -*- mode:c++ -*-
+// Copyright (c) 2013 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder. You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
// Copyright (c) 2003-2006 The Regents of The University of Michigan
// All rights reserved.
//
@@ -929,7 +941,14 @@ decode OPCODE default Unknown::unknown() {
PseudoInst::arm(xc->tcBase());
}}, IsNonSpeculative);
0x01: quiesce({{
- PseudoInst::quiesce(xc->tcBase());
+ // Don't sleep if (unmasked) interrupts are pending
+ Interrupts* interrupts =
+ xc->tcBase()->getCpuPtr()->getInterruptController();
+ if (interrupts->checkInterrupts(xc->tcBase())) {
+ PseudoInst::quiesceSkip(xc->tcBase());
+ } else {
+ PseudoInst::quiesce(xc->tcBase());
+ }
}}, IsNonSpeculative, IsQuiesce);
0x02: quiesceNs({{
PseudoInst::quiesceNs(xc->tcBase(), R16);