Faults: Replace calls to genMachineCheckFault with M5PanicFault.

2 files changed, 7 insertions, 9 deletions

diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh
index edac1cda6..3da97ccb4 100644
--- a/src/arch/alpha/faults.hh
+++ b/src/arch/alpha/faults.hh
@@ -84,11 +84,6 @@ class AlignmentFault : public AlphaFault
     bool isAlignmentFault() const {return true;}
 };
 
-static inline Fault genMachineCheckFault()
-{
-    return new MachineCheckFault;
-}
-
 class ResetFault : public AlphaFault
 {
   private:
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index fbe188973..b211c4923 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -36,6 +36,7 @@
 #include "arch/alpha/faults.hh"
 #include "arch/alpha/pagetable.hh"
 #include "arch/alpha/tlb.hh"
+#include "arch/generic/debugfaults.hh"
 #include "base/inifile.hh"
 #include "base/str.hh"
 #include "base/trace.hh"
@@ -434,8 +435,9 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
     }
 
     // check that the physical address is ok (catch bad physical addresses)
-    if (req->getPaddr() & ~PAddrImplMask)
-        return genMachineCheckFault();
+    if (req->getPaddr() & ~PAddrImplMask) {
+        return new MachineCheckFault();
+    }
 
     return checkCacheability(req, true);
 
@@ -562,8 +564,9 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
     }
 
     // check that the physical address is ok (catch bad physical addresses)
-    if (req->getPaddr() & ~PAddrImplMask)
-        return genMachineCheckFault();
+    if (req->getPaddr() & ~PAddrImplMask) {
+        return new MachineCheckFault();
+    }
 
     return checkCacheability(req);
 }