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| author | Nathan Binkert <nate@binkert.org> | 2008-09-27 21:03:49 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2008-09-27 21:03:49 -0700 |
| commit | 80d9be86e616e819cc3c9a0bbc8a42a5beb41247 (patch) | |
| tree | 311a579c3be054b5dfb603ac6040af3027d416a2 /src/arch/alpha | |
| parent | cf7ddd8e8ac92cf5b90cd89a028414dd782c645a (diff) | |
| download | gem5-80d9be86e616e819cc3c9a0bbc8a42a5beb41247.tar.xz | |
gcc: Add extra parens to quell warnings.
Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off. Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
Diffstat (limited to 'src/arch/alpha')
| -rw-r--r-- | src/arch/alpha/ev5.hh | 4 | ||||
| -rw-r--r-- | src/arch/alpha/pagetable.hh | 4 | ||||
| -rw-r--r-- | src/arch/alpha/utility.hh | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/alpha/ev5.hh b/src/arch/alpha/ev5.hh index 4c4f282f1..1915d822b 100644 --- a/src/arch/alpha/ev5.hh +++ b/src/arch/alpha/ev5.hh @@ -80,7 +80,7 @@ Phys2K0Seg(Addr addr) inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } inline Addr DTB_PTE_PPN(uint64_t reg) -{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; } +{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); } inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } @@ -90,7 +90,7 @@ inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } inline Addr ITB_PTE_PPN(uint64_t reg) -{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; } +{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); } inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } diff --git a/src/arch/alpha/pagetable.hh b/src/arch/alpha/pagetable.hh index 4f7beb19b..6cf11be56 100644 --- a/src/arch/alpha/pagetable.hh +++ b/src/arch/alpha/pagetable.hh @@ -57,9 +57,9 @@ struct VAddr Addr level3() const { return PteAddr(addr >> PageShift); } Addr level2() const - { return PteAddr(addr >> NPtePageShift + PageShift); } + { return PteAddr(addr >> (NPtePageShift + PageShift)); } Addr level1() const - { return PteAddr(addr >> 2 * NPtePageShift + PageShift); } + { return PteAddr(addr >> (2 * NPtePageShift + PageShift)); } }; struct PageTableEntry diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index 84f7cc487..76c6c5726 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -53,14 +53,14 @@ inline bool isCallerSaveIntegerRegister(unsigned int reg) { panic("register classification not implemented"); - return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); + return (reg >= 1 && reg <= 8) || (reg >= 22 && reg <= 25) || reg == 27; } inline bool isCalleeSaveIntegerRegister(unsigned int reg) { panic("register classification not implemented"); - return (reg >= 9 && reg <= 15); + return reg >= 9 && reg <= 15; } inline bool |