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authorSteve Reinhardt <stever@eecs.umich.edu>2006-11-12 22:04:00 -0800
committerSteve Reinhardt <stever@eecs.umich.edu>2006-11-12 22:04:00 -0800
commit51d8c59ef8bddb1078d2f010c143ae9471c60c2d (patch)
tree2906de128175b791419187c0cc9e6342837984d3 /src/arch/alpha
parent4c21fab575b146c0e9d374c352124c4d626fec00 (diff)
parent0f633c5fee2a371bc216ca71192c6ff02dcc3b5c (diff)
downloadgem5-51d8c59ef8bddb1078d2f010c143ae9471c60c2d.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into vm1.(none):/home/stever/bk/newmem-head --HG-- extra : convert_revision : faab7569deefde94c20133b2f70a8567bcaa2960
Diffstat (limited to 'src/arch/alpha')
-rw-r--r--src/arch/alpha/miscregfile.cc10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc
index 4cf57a690..962d4609f 100644
--- a/src/arch/alpha/miscregfile.cc
+++ b/src/arch/alpha/miscregfile.cc
@@ -132,7 +132,6 @@ namespace AlphaISA
MiscRegFile::setRegWithEffect(int misc_reg, const MiscReg &val,
ThreadContext *tc)
{
-#if FULL_SYSTEM
switch(misc_reg) {
case MISCREG_FPCR:
fpcr = val;
@@ -150,12 +149,13 @@ namespace AlphaISA
intr_flag = val;
return;
default:
- return setIpr(misc_reg, val, tc);
- }
+#if FULL_SYSTEM
+ setIpr(misc_reg, val, tc);
#else
- //panic("No registers with side effects in SE mode!");
- return;
+ panic("No registers with side effects in SE mode!");
#endif
+ return;
+ }
}
}