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authorSteve Reinhardt <stever@eecs.umich.edu>2007-02-12 09:27:32 -0800
committerSteve Reinhardt <stever@eecs.umich.edu>2007-02-12 09:27:32 -0800
commitad17b3265178deacb2dce7a98033575c0e98f518 (patch)
treefb837d9a9afa07d4167e94a7920d34a42a3e0171 /src/arch/alpha
parentda1ad46482d80ae45982dc23c09ff13e5d490087 (diff)
parentf78bc80bd75f6f4ebf080620b3aaeaee3b3e46cc (diff)
downloadgem5-ad17b3265178deacb2dce7a98033575c0e98f518.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into vm1.(none):/home/stever/bk/newmem-head --HG-- extra : convert_revision : 496428e23050122a8a0029e5fddea261bef5729e
Diffstat (limited to 'src/arch/alpha')
-rw-r--r--src/arch/alpha/isa/decoder.isa9
-rw-r--r--src/arch/alpha/isa/mem.isa75
-rw-r--r--src/arch/alpha/locked_mem.hh8
3 files changed, 88 insertions, 4 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 6df47ef7a..1da6a60f1 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -84,6 +84,9 @@ decode OPCODE default Unknown::unknown() {
uint64_t tmp = write_result;
// see stq_c
Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
+ if (tmp == 1) {
+ xc->setStCondFailures(0);
+ }
}}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
0x2f: stq_c({{ Mem.uq = Ra; }},
{{
@@ -96,6 +99,12 @@ decode OPCODE default Unknown::unknown() {
// mailbox access, and we don't update the
// result register at all.
Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
+ if (tmp == 1) {
+ // clear failure counter... this is
+ // non-architectural and for debugging
+ // only.
+ xc->setStCondFailures(0);
+ }
}}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
}
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index c0bdd2c05..3a177d990 100644
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -350,6 +350,41 @@ def template StoreMemAccExecute {{
{
Addr EA;
Fault fault = NoFault;
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_rd)s;
+ EA = xc->getEA();
+
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
+ memAccessFlags, NULL);
+ if (traceData) { traceData->setData(Mem); }
+ }
+
+ if (fault == NoFault) {
+ %(postacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+
+ return fault;
+ }
+}};
+
+def template StoreCondMemAccExecute {{
+ Fault
+ %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@@ -386,6 +421,40 @@ def template StoreExecute {{
{
Addr EA;
Fault fault = NoFault;
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
+ memAccessFlags, NULL);
+ if (traceData) { traceData->setData(Mem); }
+ }
+
+ if (fault == NoFault) {
+ %(postacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+
+ return fault;
+ }
+}};
+
+def template StoreCondExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@@ -614,10 +683,8 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
# select templates
- # define aliases... most StoreCond templates are the same as the
- # corresponding Store templates (only CompleteAcc is different).
- StoreCondMemAccExecute = StoreMemAccExecute
- StoreCondExecute = StoreExecute
+ # The InitiateAcc template is the same for StoreCond templates as the
+ # corresponding Store template..
StoreCondInitiateAcc = StoreInitiateAcc
memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index 52fe24173..be5086bd7 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -35,6 +35,14 @@
* @file
*
* ISA-specific helper functions for locked memory accesses.
+ *
+ * Note that these functions are not embedded in the ISA description
+ * because they operate on the *physical* address rather than the
+ * virtual address. In the current M5 design, the physical address is
+ * not accessible from the ISA description, only from the CPU model.
+ * Thus the CPU is responsible for calling back to the ISA (here)
+ * after the address translation has been performed to allow the ISA
+ * to do these manipulations based on the physical address.
*/
#include "arch/alpha/miscregfile.hh"