arch: Use shared_ptr for all Faults

This patch takes quite a large step in transitioning from the ad-hoc
RefCountingPtr to the c++11 shared_ptr by adopting its use for all
Faults. There are no changes in behaviour, and the code modifications
are mostly just replacing "new" with "make_shared".

10 files changed, 60 insertions, 44 deletions

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 4dcc58ffe..d66ab42aa 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -477,7 +477,7 @@ SimpleThread::hwrei()
 {
     PCState pc = pcState();
     if (!(pc.pc() & 0x3))
-        return new UnimplementedOpcodeFault;
+        return std::make_shared<UnimplementedOpcodeFault>();
 
     pc.npc(readMiscRegNoEffect(IPR_EXC_ADDR));
     pcState(pc);
diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh
index 4a5e036fd..005d8af8a 100644
--- a/src/arch/alpha/faults.hh
+++ b/src/arch/alpha/faults.hh
@@ -48,6 +48,7 @@ class AlphaFault : public FaultBase
     virtual bool skipFaultingInstruction() {return false;}
     virtual bool setRestartAddress() {return true;}
   public:
+    virtual ~AlphaFault() {}
     void invoke(ThreadContext * tc, const StaticInstPtr &inst =
                 StaticInst::nullStaticInstPtr);
     virtual FaultVect vect() = 0;
diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index 5749a1f0d..3e9c90381 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -32,6 +32,8 @@
 #ifndef __ARCH_ALPHA_INTERRUPT_HH__
 #define __ARCH_ALPHA_INTERRUPT_HH__
 
+#include <memory>
+
 #include "arch/alpha/faults.hh"
 #include "arch/alpha/isa_traits.hh"
 #include "base/compiler.hh"
@@ -176,7 +178,7 @@ class Interrupts : public SimObject
             DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
                     tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
 
-            return new InterruptFault;
+            return std::make_shared<InterruptFault>();
         } else {
             return NoFault;
         }
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 93863b50d..c77ca434f 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -120,7 +120,7 @@ decode OPCODE default Unknown::unknown() {
                 // signed overflow occurs when operands have same sign
                 // and sign of result does not match.
                 if (Ra_sl<31:> == Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
-                    fault = new IntegerOverflowFault;
+                    fault = std::make_shared<IntegerOverflowFault>();
                 Rc_sl = tmp;
             }});
             0x02: s4addl({{ Rc_sl = (Ra_sl << 2) + Rb_or_imm_sl; }});
@@ -132,7 +132,7 @@ decode OPCODE default Unknown::unknown() {
                 // signed overflow occurs when operands have same sign
                 // and sign of result does not match.
                 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
-                    fault = new IntegerOverflowFault;
+                    fault = std::make_shared<IntegerOverflowFault>();
                 Rc = tmp;
             }});
             0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
@@ -146,7 +146,7 @@ decode OPCODE default Unknown::unknown() {
                 // sign bit of the subtrahend (Rb), i.e., if the initial
                 // signs are the *same* then no overflow can occur
                 if (Ra_sl<31:> != Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
-                    fault = new IntegerOverflowFault;
+                    fault = std::make_shared<IntegerOverflowFault>();
                 Rc_sl = tmp;
             }});
             0x0b: s4subl({{ Rc_sl = (Ra_sl << 2) - Rb_or_imm_sl; }});
@@ -160,7 +160,7 @@ decode OPCODE default Unknown::unknown() {
                 // sign bit of the subtrahend (Rb), i.e., if the initial
                 // signs are the *same* then no overflow can occur
                 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
-                    fault = new IntegerOverflowFault;
+                    fault = std::make_shared<IntegerOverflowFault>();
                 Rc = tmp;
             }});
             0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
@@ -313,7 +313,7 @@ decode OPCODE default Unknown::unknown() {
                 // checking the upper 33 bits for all 0s or all 1s.
                 uint64_t sign_bits = tmp<63:31>;
                 if (sign_bits != 0 && sign_bits != mask(33))
-                    fault = new IntegerOverflowFault;
+                    fault = std::make_shared<IntegerOverflowFault>();
                 Rc_sl = tmp<31:0>;
             }}, IntMultOp);
             0x60: mulqv({{
@@ -324,7 +324,7 @@ decode OPCODE default Unknown::unknown() {
                 // the lower 64
                 if (!((hi == 0 && lo<63:> == 0) ||
                       (hi == mask(64) && lo<63:> == 1)))
-                    fault = new IntegerOverflowFault;
+                    fault = std::make_shared<IntegerOverflowFault>();
                 Rc = lo;
             }}, IntMultOp);
         }
@@ -603,19 +603,19 @@ decode OPCODE default Unknown::unknown() {
 #if SS_COMPATIBLE_FP
                     0x0b: sqrts({{
                         if (Fb < 0.0)
-                            fault = new ArithmeticFault;
+                            fault = std::make_shared<ArithmeticFault>();
                         Fc = sqrt(Fb);
                     }}, FloatSqrtOp);
 #else
                     0x0b: sqrts({{
                         if (Fb_sf < 0.0)
-                            fault = new ArithmeticFault;
+                            fault = std::make_shared<ArithmeticFault>();
                         Fc_sf = sqrt(Fb_sf);
                     }}, FloatSqrtOp);
 #endif
                     0x2b: sqrtt({{
                         if (Fb < 0.0)
-                            fault = new ArithmeticFault;
+                            fault = std::make_shared<ArithmeticFault>();
                         Fc = sqrt(Fb);
                     }}, FloatSqrtOp);
                 }
@@ -746,7 +746,7 @@ decode OPCODE default Unknown::unknown() {
                 // checking the upper 33 bits for all 0s or all 1s.
                 uint64_t sign_bits = Fb_uq<63:31>;
                 if (sign_bits != 0 && sign_bits != mask(33))
-                    fault = new IntegerOverflowFault;
+                    fault = std::make_shared<IntegerOverflowFault>();
                 Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
             }});
 
@@ -854,7 +854,7 @@ decode OPCODE default Unknown::unknown() {
                  && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
                 // invalid pal function code, or attempt to do privileged
                 // PAL call in non-kernel mode
-                fault = new UnimplementedOpcodeFault;
+                fault = std::make_shared<UnimplementedOpcodeFault>();
             } else {
                 // check to see if simulator wants to do something special
                 // on this PAL call (including maybe suppress it)
@@ -904,7 +904,7 @@ decode OPCODE default Unknown::unknown() {
                         IprToMiscRegIndex[ipr_index] : -1;
                 if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
                     miscRegIndex >= NumInternalProcRegs)
-                        fault = new UnimplementedOpcodeFault;
+                    fault = std::make_shared<UnimplementedOpcodeFault>();
                 else
                     Ra = xc->readMiscReg(miscRegIndex);
             }}, IsIprAccess);
@@ -919,7 +919,7 @@ decode OPCODE default Unknown::unknown() {
                         IprToMiscRegIndex[ipr_index] : -1;
                 if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) ||
                     miscRegIndex >= NumInternalProcRegs)
-                        fault = new UnimplementedOpcodeFault;
+                    fault = std::make_shared<UnimplementedOpcodeFault>();
                 else
                     xc->setMiscReg(miscRegIndex, Ra);
                 if (traceData) { traceData->setData(Ra); }
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index 78a366ed2..4d19f1421 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -46,7 +46,7 @@ output exec {{
     {
         Fault fault = NoFault;  // dummy... this ipr access should not fault
         if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
-            fault = new FloatEnableFault;
+            fault = std::make_shared<FloatEnableFault>();
         }
         return fault;
     }
diff --git a/src/arch/alpha/isa/opcdec.isa b/src/arch/alpha/isa/opcdec.isa
index 0051ea828..ceb25cd96 100644
--- a/src/arch/alpha/isa/opcdec.isa
+++ b/src/arch/alpha/isa/opcdec.isa
@@ -69,7 +69,7 @@ output exec {{
     OpcdecFault::execute(CPU_EXEC_CONTEXT *xc,
                      Trace::InstRecord *traceData) const
     {
-        return new UnimplementedOpcodeFault;
+        return std::make_shared<UnimplementedOpcodeFault>();
     }
 }};
 
diff --git a/src/arch/alpha/isa/unimp.isa b/src/arch/alpha/isa/unimp.isa
index f9643d6b4..26ec1c2bd 100644
--- a/src/arch/alpha/isa/unimp.isa
+++ b/src/arch/alpha/isa/unimp.isa
@@ -118,7 +118,7 @@ output exec {{
     {
         panic("attempt to execute unimplemented instruction '%s' "
               "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
-        return new UnimplementedOpcodeFault;
+        return std::make_shared<UnimplementedOpcodeFault>();
     }
 
     Fault
diff --git a/src/arch/alpha/isa/unknown.isa b/src/arch/alpha/isa/unknown.isa
index b2e7d2d1b..f356f24d8 100644
--- a/src/arch/alpha/isa/unknown.isa
+++ b/src/arch/alpha/isa/unknown.isa
@@ -49,7 +49,7 @@ output exec {{
     {
         panic("attempt to execute unknown instruction "
               "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
-        return new UnimplementedOpcodeFault;
+        return std::make_shared<UnimplementedOpcodeFault>();
     }
 }};
 
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index f39785ebb..44326df40 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -30,6 +30,7 @@
  *          Andrew Schultz
  */
 
+#include <memory>
 #include <string>
 #include <vector>
 
@@ -220,7 +221,8 @@ TLB::checkCacheability(RequestPtr &req, bool itb)
     if (req->getPaddr() & PAddrUncachedBit43) {
         // IPR memory space not implemented
         if (PAddrIprSpace(req->getPaddr())) {
-            return new UnimpFault("IPR memory space not implemented!");
+            return std::make_shared<UnimpFault>(
+                "IPR memory space not implemented!");
         } else {
             // mark request as uncacheable
             req->setFlags(Request::UNCACHEABLE);
@@ -233,7 +235,8 @@ TLB::checkCacheability(RequestPtr &req, bool itb)
         // we don't have a ROM and we don't want to try to fetch from a device 
         // register as we destroy any data that is clear-on-read. 
         if (req->isUncacheable() && itb) 
-            return new UnimpFault("CPU trying to fetch from uncached I/O");
+            return std::make_shared<UnimpFault>(
+                "CPU trying to fetch from uncached I/O");
 
     }
     return NoFault;
@@ -387,7 +390,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
         // verify that this is a good virtual address
         if (!validVirtualAddress(req->getVaddr())) {
             fetch_acv++;
-            return new ItbAcvFault(req->getVaddr());
+            return std::make_shared<ItbAcvFault>(req->getVaddr());
         }
 
 
@@ -398,7 +401,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
             if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
                 mode_kernel) {
                 fetch_acv++;
-                return new ItbAcvFault(req->getVaddr());
+                return std::make_shared<ItbAcvFault>(req->getVaddr());
             }
 
             req->setPaddr(req->getVaddr() & PAddrImplMask);
@@ -416,7 +419,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
 
             if (!entry) {
                 fetch_misses++;
-                return new ItbPageFault(req->getVaddr());
+                return std::make_shared<ItbPageFault>(req->getVaddr());
             }
 
             req->setPaddr((entry->ppn << PageShift) +
@@ -428,7 +431,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
                   (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) {
                 // instruction access fault
                 fetch_acv++;
-                return new ItbAcvFault(req->getVaddr());
+                return std::make_shared<ItbAcvFault>(req->getVaddr());
             }
 
             fetch_hits++;
@@ -437,7 +440,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
 
     // check that the physical address is ok (catch bad physical addresses)
     if (req->getPaddr() & ~PAddrImplMask) {
-        return new MachineCheckFault();
+        return std::make_shared<MachineCheckFault>();
     }
 
     return checkCacheability(req, true);
@@ -457,7 +460,9 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
         DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
                 req->getSize());
         uint64_t flags = write ? MM_STAT_WR_MASK : 0;
-        return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
+        return std::make_shared<DtbAlignmentFault>(req->getVaddr(),
+                                                   req->getFlags(),
+                                                   flags);
     }
 
     if (PcPAL(req->getPC())) {
@@ -476,7 +481,9 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
             uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
                 MM_STAT_BAD_VA_MASK |
                 MM_STAT_ACV_MASK;
-            return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
+            return std::make_shared<DtbPageFault>(req->getVaddr(),
+                                                  req->getFlags(),
+                                                  flags);
         }
 
         // Check for "superpage" mapping
@@ -488,8 +495,9 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
                 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
                                   MM_STAT_ACV_MASK);
 
-                return new DtbAcvFault(req->getVaddr(), req->getFlags(),
-                                       flags);
+                return std::make_shared<DtbAcvFault>(req->getVaddr(),
+                                                     req->getFlags(),
+                                                     flags);
             }
 
             req->setPaddr(req->getVaddr() & PAddrImplMask);
@@ -516,10 +524,12 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
                 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
                     MM_STAT_DTB_MISS_MASK;
                 return (req->getFlags() & Request::VPTE) ?
-                    (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
-                                              flags)) :
-                    (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
-                                              flags));
+                    (Fault)(std::make_shared<PDtbMissFault>(req->getVaddr(),
+                                                            req->getFlags(),
+                                                            flags)) :
+                    (Fault)(std::make_shared<NDtbMissFault>(req->getVaddr(),
+                                                            req->getFlags(),
+                                                            flags));
             }
 
             req->setPaddr((entry->ppn << PageShift) +
@@ -532,28 +542,32 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
                     uint64_t flags = MM_STAT_WR_MASK |
                         MM_STAT_ACV_MASK |
                         (entry->fonw ? MM_STAT_FONW_MASK : 0);
-                    return new DtbPageFault(req->getVaddr(), req->getFlags(),
-                                            flags);
+                    return std::make_shared<DtbPageFault>(req->getVaddr(),
+                                                          req->getFlags(),
+                                                          flags);
                 }
                 if (entry->fonw) {
                     write_acv++;
                     uint64_t flags = MM_STAT_WR_MASK | MM_STAT_FONW_MASK;
-                    return new DtbPageFault(req->getVaddr(), req->getFlags(),
-                                            flags);
+                    return std::make_shared<DtbPageFault>(req->getVaddr(),
+                                                          req->getFlags(),
+                                                          flags);
                 }
             } else {
                 if (!(entry->xre & MODE2MASK(mode))) {
                     read_acv++;
                     uint64_t flags = MM_STAT_ACV_MASK |
                         (entry->fonr ? MM_STAT_FONR_MASK : 0);
-                    return new DtbAcvFault(req->getVaddr(), req->getFlags(),
-                                           flags);
+                    return std::make_shared<DtbAcvFault>(req->getVaddr(),
+                                                         req->getFlags(),
+                                                         flags);
                 }
                 if (entry->fonr) {
                     read_acv++;
                     uint64_t flags = MM_STAT_FONR_MASK;
-                    return new DtbPageFault(req->getVaddr(), req->getFlags(),
-                                            flags);
+                    return std::make_shared<DtbPageFault>(req->getVaddr(),
+                                                          req->getFlags(),
+                                                          flags);
                 }
             }
         }
@@ -566,7 +580,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
 
     // check that the physical address is ok (catch bad physical addresses)
     if (req->getPaddr() & ~PAddrImplMask) {
-        return new MachineCheckFault();
+        return std::make_shared<MachineCheckFault>();
     }
 
     return checkCacheability(req);
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 91394e972..ee59041f3 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -42,7 +42,6 @@
 #include "base/statistics.hh"
 #include "mem/request.hh"
 #include "params/AlphaTLB.hh"
-#include "sim/fault_fwd.hh"
 #include "sim/tlb.hh"
 
 class ThreadContext;