CPU: Merge the predecoder and decoder.

These classes are always used together, and merging them will give the ISAs
more flexibility in how they cache things and manage the process.

--HG--
rename : src/arch/x86/predecoder_tables.cc => src/arch/x86/decoder_tables.cc

3 files changed, 67 insertions, 113 deletions

diff --git a/src/arch/alpha/decoder.hh b/src/arch/alpha/decoder.hh
index a41ed06bb..4233c2d44 100644
--- a/src/arch/alpha/decoder.hh
+++ b/src/arch/alpha/decoder.hh
@@ -34,6 +34,7 @@
 #include "arch/types.hh"
 #include "cpu/decode_cache.hh"
 #include "cpu/static_inst_fwd.hh"
+#include "sim/full_system.hh"
 
 namespace AlphaISA
 {
@@ -41,6 +42,62 @@ namespace AlphaISA
 class Decoder
 {
   protected:
+    ThreadContext *tc;
+
+    // The extended machine instruction being generated
+    ExtMachInst ext_inst;
+    bool instDone;
+
+  public:
+    Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
+    {}
+
+    ThreadContext *
+    getTC()
+    {
+        return tc;
+    }
+
+    void
+    setTC(ThreadContext * _tc)
+    {
+        tc = _tc;
+    }
+
+    void
+    process()
+    { }
+
+    void
+    reset()
+    {
+        instDone = false;
+    }
+
+    // Use this to give data to the predecoder. This should be used
+    // when there is control flow.
+    void
+    moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
+    {
+        ext_inst = inst;
+        instDone = true;
+        if (FullSystem)
+            ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
+    }
+
+    bool
+    needMoreBytes()
+    {
+        return true;
+    }
+
+    bool
+    instReady()
+    {
+        return instDone;
+    }
+
+  protected:
     /// A cache of decoded instruction objects.
     static DecodeCache defaultCache;
 
@@ -55,6 +112,15 @@ class Decoder
     {
         return defaultCache.decode(this, mach_inst, addr);
     }
+
+    StaticInstPtr
+    decode(AlphaISA::PCState &nextPC)
+    {
+        if (!instDone)
+            return NULL;
+        instDone = false;
+        return decode(ext_inst, nextPC.instAddr());
+    }
 };
 
 } // namespace AlphaISA
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 1bc00e753..cb43c1357 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -73,6 +73,7 @@ using namespace AlphaISA;
 output exec {{
 #include <cmath>
 
+#include "arch/alpha/decoder.hh"
 #include "arch/alpha/registers.hh"
 #include "arch/alpha/regredir.hh"
 #include "arch/generic/memhelpers.hh"
diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh
deleted file mode 100644
index a08cddaec..000000000
--- a/src/arch/alpha/predecoder.hh
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#ifndef __ARCH_ALPHA_PREDECODER_HH__
-#define __ARCH_ALPHA_PREDECODER_HH__
-
-#include "arch/alpha/types.hh"
-#include "base/misc.hh"
-#include "base/types.hh"
-#include "sim/full_system.hh"
-
-class ThreadContext;
-
-namespace AlphaISA {
-
-class Predecoder
-{
-  protected:
-    ThreadContext *tc;
-
-    // The extended machine instruction being generated
-    ExtMachInst ext_inst;
-    bool emiIsReady;
-
-  public:
-    Predecoder(ThreadContext * _tc)
-        : tc(_tc), emiIsReady(false)
-    {}
-
-    ThreadContext *
-    getTC()
-    {
-        return tc;
-    }
-
-    void
-    setTC(ThreadContext * _tc)
-    {
-        tc = _tc;
-    }
-
-    void
-    process()
-    { }
-
-    void
-    reset()
-    {
-        emiIsReady = false;
-    }
-
-    // Use this to give data to the predecoder. This should be used
-    // when there is control flow.
-    void
-    moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
-    {
-        ext_inst = inst;
-        emiIsReady = true;
-        if (FullSystem)
-            ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
-    }
-
-    bool
-    needMoreBytes()
-    {
-        return true;
-    }
-
-    bool
-    extMachInstReady()
-    {
-        return emiIsReady;
-    }
-
-    // This returns a constant reference to the ExtMachInst to avoid a copy
-    const ExtMachInst &
-    getExtMachInst(PCState &pc)
-    {
-        emiIsReady = false;
-        return ext_inst;
-    }
-};
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_PREDECODER_HH__