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authorGabe Black <gblack@eecs.umich.edu>2011-09-19 02:40:19 -0700
committerGabe Black <gblack@eecs.umich.edu>2011-09-19 02:40:19 -0700
commit83aa47adca17be33d53da6734ea422e1e0e2a07c (patch)
tree7241093033fd9d6e07ac30d7439f0589b7a25642 /src/arch/alpha
parent9eda6b1d88a4bdd466964065dd6009bdcedfcb92 (diff)
downloadgem5-83aa47adca17be33d53da6734ea422e1e0e2a07c.tar.xz
PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.
Diffstat (limited to 'src/arch/alpha')
-rw-r--r--src/arch/alpha/isa/decoder.isa8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 359c6b3b2..d0aa13d38 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -944,7 +944,6 @@ decode OPCODE default Unknown::unknown() {
format BasicOperate {
// M5 special opcodes use the reserved 0x01 opcode space
0x01: decode M5FUNC {
-#if FULL_SYSTEM
0x00: arm({{
PseudoInst::arm(xc->tcBase());
}}, IsNonSpeculative);
@@ -960,7 +959,6 @@ decode OPCODE default Unknown::unknown() {
0x04: quiesceTime({{
R0 = PseudoInst::quiesceTime(xc->tcBase());
}}, IsNonSpeculative, IsUnverifiable);
-#endif
0x07: rpns({{
R0 = PseudoInst::rpns(xc->tcBase());
}}, IsNonSpeculative, IsUnverifiable);
@@ -980,14 +978,12 @@ decode OPCODE default Unknown::unknown() {
0x21: m5exit({{
PseudoInst::m5exit(xc->tcBase(), R16);
}}, No_OpClass, IsNonSpeculative);
-#if FULL_SYSTEM
0x31: loadsymbol({{
PseudoInst::loadsymbol(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
0x30: initparam({{
Ra = PseudoInst::initParam(xc->tcBase());
}});
-#endif
0x40: resetstats({{
PseudoInst::resetstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
@@ -1000,22 +996,18 @@ decode OPCODE default Unknown::unknown() {
0x43: m5checkpoint({{
PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
-#if FULL_SYSTEM
0x50: m5readfile({{
R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
}}, IsNonSpeculative);
-#endif
0x51: m5break({{
PseudoInst::debugbreak(xc->tcBase());
}}, IsNonSpeculative);
0x52: m5switchcpu({{
PseudoInst::switchcpu(xc->tcBase());
}}, IsNonSpeculative);
-#if FULL_SYSTEM
0x53: m5addsymbol({{
PseudoInst::addsymbol(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
-#endif
0x54: m5panic({{
panic("M5 panic instruction called at pc = %#x.", PC);
}}, IsNonSpeculative);