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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-10-20 16:39:47 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-10-20 16:39:47 -0400 |
| commit | 0b5cf4ba6eb2702ade2bc77c07842edd97eab264 (patch) | |
| tree | 4e1ed8130794049e771759059269e6dc23848180 /src/arch/alpha | |
| parent | 76c07ea46bc4f8f6d500f909abfb07addf217940 (diff) | |
| parent | 6c6b78126a38cf92eef89f027312e1c7a063bd18 (diff) | |
| download | gem5-0b5cf4ba6eb2702ade2bc77c07842edd97eab264.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem
--HG--
extra : convert_revision : 2711fec2bf72801999b060e65f0bf744c18734fb
Diffstat (limited to 'src/arch/alpha')
| -rw-r--r-- | src/arch/alpha/isa/main.isa | 11 | ||||
| -rw-r--r-- | src/arch/alpha/isa/mem.isa | 10 |
2 files changed, 12 insertions, 9 deletions
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index 1270bf8d8..2024b1117 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -45,20 +45,22 @@ output header {{ #include <iostream> #include <iomanip> +#include "arch/alpha/faults.hh" #include "config/ss_compatible_fp.hh" #include "cpu/static_inst.hh" -#include "arch/alpha/faults.hh" #include "mem/request.hh" // some constructors use MemReq flags +#include "mem/packet.hh" }}; output decoder {{ +#include <cmath> + #include "base/cprintf.hh" #include "base/fenv.hh" #include "base/loader/symtab.hh" #include "config/ss_compatible_fp.hh" #include "cpu/thread_context.hh" // for Jump::branchTarget() - -#include <math.h> +#include "mem/packet.hh" using namespace AlphaISA; }}; @@ -73,8 +75,9 @@ output exec {{ #include "config/ss_compatible_fp.hh" #include "cpu/base.hh" #include "cpu/exetrace.hh" +#include "mem/packet.hh" +#include "mem/packet_access.hh" #include "sim/sim_exit.hh" -#include "mem/packet_impl.hh" using namespace AlphaISA; }}; diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa index fe69c36a5..02291ed6b 100644 --- a/src/arch/alpha/isa/mem.isa +++ b/src/arch/alpha/isa/mem.isa @@ -186,7 +186,7 @@ def template InitiateAccDeclare {{ def template CompleteAccDeclare {{ - Fault completeAcc(Packet *, %(CPU_exec_context)s *, + Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; }}; @@ -313,7 +313,7 @@ def template LoadInitiateAcc {{ def template LoadCompleteAcc {{ - Fault %(class_name)s::completeAcc(Packet *pkt, + Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -437,7 +437,7 @@ def template StoreInitiateAcc {{ def template StoreCompleteAcc {{ - Fault %(class_name)s::completeAcc(Packet *pkt, + Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -460,7 +460,7 @@ def template StoreCompleteAcc {{ def template StoreCondCompleteAcc {{ - Fault %(class_name)s::completeAcc(Packet *pkt, + Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -535,7 +535,7 @@ def template MiscInitiateAcc {{ def template MiscCompleteAcc {{ - Fault %(class_name)s::completeAcc(Packet *pkt, + Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { |