diff options
| author | Nathan Binkert <nate@binkert.org> | 2009-05-26 09:23:13 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2009-05-26 09:23:13 -0700 |
| commit | 47877cf2dbd6ee2f1cf9b2c609d37b0589e876ca (patch) | |
| tree | 6beb00dfe7e31b9bf82f7aba4710b0c487b6543f /src/arch/alpha | |
| parent | d93392df28fc6c9a5c70fb6252a12afdc72d9344 (diff) | |
| download | gem5-47877cf2dbd6ee2f1cf9b2c609d37b0589e876ca.tar.xz | |
types: add a type for thread IDs and try to use it everywhere
Diffstat (limited to 'src/arch/alpha')
| -rw-r--r-- | src/arch/alpha/miscregfile.cc | 8 | ||||
| -rw-r--r-- | src/arch/alpha/miscregfile.hh | 13 |
2 files changed, 11 insertions, 10 deletions
diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc index 5dc316a83..d52d900fd 100644 --- a/src/arch/alpha/miscregfile.cc +++ b/src/arch/alpha/miscregfile.cc @@ -65,7 +65,7 @@ MiscRegFile::MiscRegFile(BaseCPU *_cpu) MiscReg -MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid ) +MiscRegFile::readRegNoEffect(int misc_reg, ThreadID tid) { switch (misc_reg) { case MISCREG_FPCR: @@ -85,7 +85,7 @@ MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid ) } MiscReg -MiscRegFile::readReg(int misc_reg, ThreadContext *tc, unsigned tid ) +MiscRegFile::readReg(int misc_reg, ThreadContext *tc, ThreadID tid) { switch (misc_reg) { case MISCREG_FPCR: @@ -104,7 +104,7 @@ MiscRegFile::readReg(int misc_reg, ThreadContext *tc, unsigned tid ) } void -MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid) +MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) { switch (misc_reg) { case MISCREG_FPCR: @@ -131,7 +131,7 @@ MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid) void MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc, - unsigned tid) + ThreadID tid) { switch (misc_reg) { case MISCREG_FPCR: diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh index 1a215b8e4..0d95e5a6d 100644 --- a/src/arch/alpha/miscregfile.hh +++ b/src/arch/alpha/miscregfile.hh @@ -88,11 +88,12 @@ class MiscRegFile int getInstAsid(); int getDataAsid(); - MiscReg readRegNoEffect(int misc_reg, unsigned tid = 0); - MiscReg readReg(int misc_reg, ThreadContext *tc, unsigned tid = 0); + MiscReg readRegNoEffect(int misc_reg, ThreadID tid = 0); + MiscReg readReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); - void setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0); - void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc, unsigned tid = 0); + void setRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0); + void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc, + ThreadID tid = 0); void clear() @@ -107,12 +108,12 @@ class MiscRegFile void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); - void reset(std::string core_name, unsigned num_threads, + void reset(std::string core_name, ThreadID num_threads, unsigned num_vpes, BaseCPU *_cpu) { } - void expandForMultithreading(unsigned num_threads, unsigned num_vpes) + void expandForMultithreading(ThreadID num_threads, unsigned num_vpes) { } |