Merge zizzer.eecs.umich.edu:/bk/newmem

into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem

--HG--
extra : convert_revision : d764fe37c71269a04fcede6cbf30e24262447e89

17 files changed, 90 insertions, 90 deletions

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 8d13511ac..ec5090eb8 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -62,7 +62,7 @@ AlphaISA::initCPU(ThreadContext *tc, int cpuId)
 
     AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
 
-    tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect());
+    tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
     tc->setNextPC(tc->readPC() + sizeof(MachInst));
 
     delete reset;
@@ -76,12 +76,12 @@ void
 AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
 {
     for (int i = 0; i < NumInternalProcRegs; ++i) {
-        tc->setMiscReg(i, 0);
+        tc->setMiscRegNoEffect(i, 0);
     }
 
-    tc->setMiscReg(IPR_PAL_BASE, PalBase);
-    tc->setMiscReg(IPR_MCSR, 0x6);
-    tc->setMiscReg(IPR_PALtemp16, cpuId);
+    tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
+    tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
+    tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
 }
 
 
@@ -94,13 +94,13 @@ AlphaISA::processInterrupts(CPU *cpu)
     int ipl = 0;
     int summary = 0;
 
-    if (cpu->readMiscReg(IPR_ASTRR))
+    if (cpu->readMiscRegNoEffect(IPR_ASTRR))
         panic("asynchronous traps not implemented\n");
 
-    if (cpu->readMiscReg(IPR_SIRR)) {
+    if (cpu->readMiscRegNoEffect(IPR_SIRR)) {
         for (int i = INTLEVEL_SOFTWARE_MIN;
              i < INTLEVEL_SOFTWARE_MAX; i++) {
-            if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
+            if (cpu->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
                 // See table 4-19 of the 21164 hardware reference
                 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
                 summary |= (ULL(1) << i);
@@ -121,12 +121,12 @@ AlphaISA::processInterrupts(CPU *cpu)
         }
     }
 
-    if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
-        cpu->setMiscReg(IPR_ISR, summary);
-        cpu->setMiscReg(IPR_INTID, ipl);
+    if (ipl && ipl > cpu->readMiscRegNoEffect(IPR_IPLR)) {
+        cpu->setMiscRegNoEffect(IPR_ISR, summary);
+        cpu->setMiscRegNoEffect(IPR_INTID, ipl);
         cpu->trap(new InterruptFault);
         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
-                cpu->readMiscReg(IPR_IPLR), ipl, summary);
+                cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
     }
 
 }
@@ -148,7 +148,7 @@ SimpleThread::hwrei()
     if (!(readPC() & 0x3))
         return new UnimplementedOpcodeFault;
 
-    setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
+    setNextPC(readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
 
     if (!misspeculating()) {
         if (kernelStats)
@@ -554,7 +554,7 @@ void
 AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
 {
     for (int i = 0; i < NumInternalProcRegs; ++i) {
-        dest->setMiscReg(i, src->readMiscReg(i));
+        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
     }
 }
 
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 5efcf92e4..9a8429635 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -126,15 +126,15 @@ void AlphaFault::invoke(ThreadContext * tc)
 
     // exception restart address
     if (setRestartAddress() || !(tc->readPC() & 0x3))
-        tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC());
+        tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, tc->readPC());
 
     if (skipFaultingInstruction()) {
         // traps...  skip faulting instruction.
-        tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
-                   tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
+        tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
+                   tc->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR) + 4);
     }
 
-    tc->setPC(tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
+    tc->setPC(tc->readMiscRegNoEffect(AlphaISA::IPR_PAL_BASE) + vect());
     tc->setNextPC(tc->readPC() + sizeof(MachInst));
 }
 
@@ -154,17 +154,17 @@ void DtbFault::invoke(ThreadContext * tc)
     if (!tc->misspeculating()
         && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
         // set VA register with faulting address
-        tc->setMiscReg(AlphaISA::IPR_VA, vaddr);
+        tc->setMiscRegNoEffect(AlphaISA::IPR_VA, vaddr);
 
         // set MM_STAT register flags
-        tc->setMiscReg(AlphaISA::IPR_MM_STAT,
+        tc->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT,
             (((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
              | ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
              | (flags & 0x3f)));
 
         // set VA_FORM register with faulting formatted address
-        tc->setMiscReg(AlphaISA::IPR_VA_FORM,
-            tc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
+        tc->setMiscRegNoEffect(AlphaISA::IPR_VA_FORM,
+            tc->readMiscRegNoEffect(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
     }
 
     AlphaFault::invoke(tc);
@@ -173,9 +173,9 @@ void DtbFault::invoke(ThreadContext * tc)
 void ItbFault::invoke(ThreadContext * tc)
 {
     if (!tc->misspeculating()) {
-        tc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
-        tc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
-                       tc->readMiscReg(AlphaISA::IPR_IVPTBR) |
+        tc->setMiscRegNoEffect(AlphaISA::IPR_ITB_TAG, pc);
+        tc->setMiscRegNoEffect(AlphaISA::IPR_IFAULT_VA_FORM,
+                       tc->readMiscRegNoEffect(AlphaISA::IPR_IVPTBR) |
                        (AlphaISA::VAddr(pc).vpn() << 3));
     }
 
diff --git a/src/arch/alpha/idle_event.cc b/src/arch/alpha/idle_event.cc
index 0f6806319..f0f1eab7a 100644
--- a/src/arch/alpha/idle_event.cc
+++ b/src/arch/alpha/idle_event.cc
@@ -40,6 +40,6 @@ IdleStartEvent::process(ThreadContext *tc)
 {
     if (tc->getKernelStats())
         tc->getKernelStats()->setIdleProcess(
-            tc->readMiscReg(AlphaISA::IPR_PALtemp23), tc);
+            tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp23), tc);
     remove();
 }
diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index 0500714ad..6453edf97 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -112,13 +112,13 @@ namespace AlphaISA
             int ipl = 0;
             int summary = 0;
 
-            if (tc->readMiscReg(IPR_ASTRR))
+            if (tc->readMiscRegNoEffect(IPR_ASTRR))
                 panic("asynchronous traps not implemented\n");
 
-            if (tc->readMiscReg(IPR_SIRR)) {
+            if (tc->readMiscRegNoEffect(IPR_SIRR)) {
                 for (int i = INTLEVEL_SOFTWARE_MIN;
                      i < INTLEVEL_SOFTWARE_MAX; i++) {
-                    if (tc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
+                    if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
                         // See table 4-19 of 21164 hardware reference
                         ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
                         summary |= (ULL(1) << i);
@@ -138,12 +138,12 @@ namespace AlphaISA
                 }
             }
 
-            if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) {
+            if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) {
                 newIpl = ipl;
                 newSummary = summary;
                 newInfoSet = true;
                 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
-                        tc->readMiscReg(IPR_IPLR), ipl, summary);
+                        tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
 
                 return new InterruptFault;
             } else {
@@ -154,8 +154,8 @@ namespace AlphaISA
         void updateIntrInfo(ThreadContext *tc)
         {
             assert(newInfoSet);
-            tc->setMiscReg(IPR_ISR, newSummary);
-            tc->setMiscReg(IPR_INTID, newIpl);
+            tc->setMiscRegNoEffect(IPR_ISR, newSummary);
+            tc->setMiscRegNoEffect(IPR_INTID, newIpl);
             newInfoSet = false;
         }
 
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 49c25c3c2..b62372f66 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -638,7 +638,7 @@ decode OPCODE default Unknown::unknown() {
         /* Rb is a fake dependency so here is a fun way to get
          * the parser to understand that.
          */
-                Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC) + (Rb & 0);
+                Ra = xc->readMiscReg(AlphaISA::IPR_CC) + (Rb & 0);
 
 #else
                 Ra = curTick;
@@ -690,7 +690,7 @@ decode OPCODE default Unknown::unknown() {
     0x00: CallPal::call_pal({{
         if (!palValid ||
             (palPriv
-             && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) {
+             && xc->readMiscReg(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) {
             // invalid pal function code, or attempt to do privileged
             // PAL call in non-kernel mode
             fault = new UnimplementedOpcodeFault;
@@ -701,8 +701,8 @@ decode OPCODE default Unknown::unknown() {
             bool dopal = xc->simPalCheck(palFunc);
 
             if (dopal) {
-                xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
-                NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE) + palOffset;
+                xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, NPC);
+                NPC = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + palOffset;
             }
         }
     }}, IsNonSpeculative);
@@ -760,7 +760,7 @@ decode OPCODE default Unknown::unknown() {
                     miscRegIndex >= NumInternalProcRegs)
                         fault = new UnimplementedOpcodeFault;
                 else
-                    Ra = xc->readMiscRegWithEffect(miscRegIndex);
+                    Ra = xc->readMiscReg(miscRegIndex);
             }}, IsIprAccess);
         }
     }
@@ -775,7 +775,7 @@ decode OPCODE default Unknown::unknown() {
                     miscRegIndex >= NumInternalProcRegs)
                         fault = new UnimplementedOpcodeFault;
                 else
-                    xc->setMiscRegWithEffect(miscRegIndex, Ra);
+                    xc->setMiscReg(miscRegIndex, Ra);
                 if (traceData) { traceData->setData(Ra); }
             }}, IsIprAccess);
         }
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index c845ea442..a350aa05f 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -46,7 +46,7 @@ output exec {{
     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
         Fault fault = NoFault;	// dummy... this ipr access should not fault
-        if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR))) {
+        if (!EV5::ICSR_FPE(xc->readMiscReg(AlphaISA::IPR_ICSR))) {
             fault = new FloatEnableFault;
         }
         return fault;
@@ -229,7 +229,7 @@ def template FloatingPointExecute {{
             %(code)s;
         } else {
             fesetround(getC99RoundingMode(
-                           xc->readMiscReg(AlphaISA::MISCREG_FPCR)));
+                           xc->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR)));
             %(code)s;
             fesetround(FE_TONEAREST);
         }
diff --git a/src/arch/alpha/kernel_stats.cc b/src/arch/alpha/kernel_stats.cc
index 6fc3cb72f..13dc95af7 100644
--- a/src/arch/alpha/kernel_stats.cc
+++ b/src/arch/alpha/kernel_stats.cc
@@ -150,7 +150,7 @@ Statistics::changeMode(cpu_mode newmode, ThreadContext *tc)
 void
 Statistics::mode(cpu_mode newmode, ThreadContext *tc)
 {
-    Addr pcbb = tc->readMiscReg(AlphaISA::IPR_PALtemp23);
+    Addr pcbb = tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp23);
 
     if (newmode == kernel && pcbb == idleProcess)
         newmode = idle;
diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index 56b5ba5ed..df66b92bc 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -56,8 +56,8 @@ template <class XC>
 inline void
 handleLockedRead(XC *xc, Request *req)
 {
-    xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
-    xc->setMiscReg(MISCREG_LOCKFLAG, true);
+    xc->setMiscRegNoEffect(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
+    xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, true);
 }
 
 
@@ -71,13 +71,13 @@ handleLockedWrite(XC *xc, Request *req)
         req->setExtraData(2);
     } else {
         // standard store conditional
-        bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
-        Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
+        bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LOCKFLAG);
+        Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LOCKADDR);
         if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
             // Lock flag not set or addr mismatch in CPU;
             // don't even bother sending to memory system
             req->setExtraData(0);
-            xc->setMiscReg(MISCREG_LOCKFLAG, false);
+            xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, false);
             // the rest of this code is not architectural;
             // it's just a debugging aid to help detect
             // livelock by warning on long sequences of failed
diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc
index 67f6c98e4..1af97adcf 100644
--- a/src/arch/alpha/miscregfile.cc
+++ b/src/arch/alpha/miscregfile.cc
@@ -61,7 +61,7 @@ namespace AlphaISA
     }
 
     MiscReg
-    MiscRegFile::readReg(int misc_reg)
+    MiscRegFile::readRegNoEffect(int misc_reg)
     {
         switch(misc_reg) {
           case MISCREG_FPCR:
@@ -87,7 +87,7 @@ namespace AlphaISA
     }
 
     MiscReg
-    MiscRegFile::readRegWithEffect(int misc_reg, ThreadContext *tc)
+    MiscRegFile::readReg(int misc_reg, ThreadContext *tc)
     {
         switch(misc_reg) {
           case MISCREG_FPCR:
@@ -112,7 +112,7 @@ namespace AlphaISA
     }
 
     void
-    MiscRegFile::setReg(int misc_reg, const MiscReg &val)
+    MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val)
     {
         switch(misc_reg) {
           case MISCREG_FPCR:
@@ -143,7 +143,7 @@ namespace AlphaISA
     }
 
     void
-    MiscRegFile::setRegWithEffect(int misc_reg, const MiscReg &val,
+    MiscRegFile::setReg(int misc_reg, const MiscReg &val,
             ThreadContext *tc)
     {
         switch(misc_reg) {
diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh
index 31b3e59b3..aea702849 100644
--- a/src/arch/alpha/miscregfile.hh
+++ b/src/arch/alpha/miscregfile.hh
@@ -75,18 +75,18 @@ namespace AlphaISA
 #endif
         }
 
-        MiscReg readReg(int misc_reg);
+        MiscReg readRegNoEffect(int misc_reg);
 
-        MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc);
+        MiscReg readReg(int misc_reg, ThreadContext *tc);
 
         //These functions should be removed once the simplescalar cpu model
         //has been replaced.
         int getInstAsid();
         int getDataAsid();
 
-        void setReg(int misc_reg, const MiscReg &val);
+        void setRegNoEffect(int misc_reg, const MiscReg &val);
 
-        void setRegWithEffect(int misc_reg, const MiscReg &val,
+        void setReg(int misc_reg, const MiscReg &val,
                 ThreadContext *tc);
 
         void clear()
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc
index 92e1b07df..3b42ca9bc 100644
--- a/src/arch/alpha/regfile.cc
+++ b/src/arch/alpha/regfile.cc
@@ -85,14 +85,14 @@ namespace AlphaISA
     void
     copyMiscRegs(ThreadContext *src, ThreadContext *dest)
     {
-        dest->setMiscReg(AlphaISA::MISCREG_FPCR,
-                src->readMiscReg(AlphaISA::MISCREG_FPCR));
-        dest->setMiscReg(AlphaISA::MISCREG_UNIQ,
-                src->readMiscReg(AlphaISA::MISCREG_UNIQ));
-        dest->setMiscReg(AlphaISA::MISCREG_LOCKFLAG,
-                src->readMiscReg(AlphaISA::MISCREG_LOCKFLAG));
-        dest->setMiscReg(AlphaISA::MISCREG_LOCKADDR,
-                src->readMiscReg(AlphaISA::MISCREG_LOCKADDR));
+        dest->setMiscRegNoEffect(AlphaISA::MISCREG_FPCR,
+                src->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR));
+        dest->setMiscRegNoEffect(AlphaISA::MISCREG_UNIQ,
+                src->readMiscRegNoEffect(AlphaISA::MISCREG_UNIQ));
+        dest->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG,
+                src->readMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG));
+        dest->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR,
+                src->readMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR));
 
 #if FULL_SYSTEM
         copyIprs(src, dest);
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index 54372da36..b93707181 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -106,25 +106,25 @@ namespace AlphaISA
             miscRegFile.clear();
         }
 
-        MiscReg readMiscReg(int miscReg)
+        MiscReg readMiscRegNoEffect(int miscReg)
         {
-            return miscRegFile.readReg(miscReg);
+            return miscRegFile.readRegNoEffect(miscReg);
         }
 
-        MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc)
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc)
         {
-            return miscRegFile.readRegWithEffect(miscReg, tc);
+            return miscRegFile.readReg(miscReg, tc);
         }
 
-        void setMiscReg(int miscReg, const MiscReg &val)
+        void setMiscRegNoEffect(int miscReg, const MiscReg &val)
         {
-            miscRegFile.setReg(miscReg, val);
+            miscRegFile.setRegNoEffect(miscReg, val);
         }
 
-        void setMiscRegWithEffect(int miscReg, const MiscReg &val,
+        void setMiscReg(int miscReg, const MiscReg &val,
                 ThreadContext * tc)
         {
-            miscRegFile.setRegWithEffect(miscReg, val, tc);
+            miscRegFile.setReg(miscReg, val, tc);
         }
 
         FloatReg readFloatReg(int floatReg)
diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc
index 4637bd7a6..a68e5218e 100644
--- a/src/arch/alpha/remote_gdb.cc
+++ b/src/arch/alpha/remote_gdb.cc
@@ -187,7 +187,7 @@ RemoteGDB::acc(Addr va, size_t len)
         if (AlphaISA::PcPAL(va) || va < 0x10000)
             return true;
 
-        Addr ptbr = context->readMiscReg(AlphaISA::IPR_PALtemp20);
+        Addr ptbr = context->readMiscRegNoEffect(AlphaISA::IPR_PALtemp20);
         TheISA::PageTableEntry pte = TheISA::kernel_pte_lookup(context->getPhysPort(), ptbr, va);
         if (!pte.valid()) {
             DPRINTF(GDBAcc, "acc:   %#x pte is invalid\n", va);
diff --git a/src/arch/alpha/stacktrace.cc b/src/arch/alpha/stacktrace.cc
index c4612e156..c16498e72 100644
--- a/src/arch/alpha/stacktrace.cc
+++ b/src/arch/alpha/stacktrace.cc
@@ -146,7 +146,7 @@ namespace AlphaISA
     {
         tc = _tc;
 
-        bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+        bool usermode = (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
 
         Addr pc = tc->readNextPC();
         bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
@@ -219,22 +219,22 @@ namespace AlphaISA
     bool
     StackTrace::isEntry(Addr addr)
     {
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp12))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp7))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp11))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp21))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp9))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp2))
             return true;
 
         return false;
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 1e0155138..3ab65e664 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -312,14 +312,14 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) const
         // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
         // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
 #if ALPHA_TLASER
-        if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
+        if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
             VAddrSpaceEV5(req->getVaddr()) == 2)
 #else
         if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
 #endif
         {
             // only valid in kernel mode
-            if (ICM_CM(tc->readMiscReg(IPR_ICM)) !=
+            if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
                 mode_kernel) {
                 acv++;
                 return new ItbAcvFault(req->getVaddr());
@@ -337,7 +337,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) const
 
         } else {
             // not a physical address: need to look up pte
-            int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN));
+            int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
             PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
                               asn);
 
@@ -352,7 +352,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) const
 
             // check permissions for this access
             if (!(pte->xre &
-                  (1 << ICM_CM(tc->readMiscReg(IPR_ICM))))) {
+                  (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) {
                 // instruction access fault
                 acv++;
                 return new ItbAcvFault(req->getVaddr());
@@ -453,7 +453,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
     Addr pc = tc->readPC();
 
     mode_type mode =
-        (mode_type)DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM));
+        (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
 
 
     /**
@@ -469,7 +469,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
     if (PcPAL(pc)) {
         mode = (req->getFlags() & ALTMODE) ?
             (mode_type)ALT_MODE_AM(
-                tc->readMiscReg(IPR_ALT_MODE))
+                tc->readMiscRegNoEffect(IPR_ALT_MODE))
             : mode_kernel;
     }
 
@@ -487,7 +487,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
 
         // Check for "superpage" mapping
 #if ALPHA_TLASER
-        if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
+        if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
             VAddrSpaceEV5(req->getVaddr()) == 2)
 #else
         if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
@@ -495,7 +495,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
         {
 
             // only valid in kernel mode
-            if (DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)) !=
+            if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) !=
                 mode_kernel) {
                 if (write) { write_acv++; } else { read_acv++; }
                 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
@@ -519,7 +519,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
             else
                 read_accesses++;
 
-            int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN));
+            int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
 
             // not a physical address: need to look up pte
             PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index 9a06cc2a4..c8a50e8a2 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -45,7 +45,7 @@ namespace AlphaISA
     static inline bool
     inUserMode(ThreadContext *tc)
     {
-        return (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+        return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
     }
 
     static inline ExtMachInst
diff --git a/src/arch/alpha/vtophys.cc b/src/arch/alpha/vtophys.cc
index 1a3147bcc..6ffbea181 100644
--- a/src/arch/alpha/vtophys.cc
+++ b/src/arch/alpha/vtophys.cc
@@ -88,7 +88,7 @@ Addr
 AlphaISA::vtophys(ThreadContext *tc, Addr addr)
 {
     AlphaISA::VAddr vaddr = addr;
-    Addr ptbr = tc->readMiscReg(AlphaISA::IPR_PALtemp20);
+    Addr ptbr = tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp20);
     Addr paddr = 0;
     //@todo Andrew couldn't remember why he commented some of this code
     //so I put it back in. Perhaps something to do with gdb debugging?