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authorSteve Reinhardt <stever@eecs.umich.edu>2006-09-01 17:12:43 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2006-09-01 17:12:43 -0700
commitabe18be544014bee31d586bf8b26ab5b622b70b7 (patch)
treead4059302f30b79257cb50cb8e51c5da38c6418c /src/arch/alpha
parentedeb8f39a7c3cbcf428743aca3017fa42865b04a (diff)
parentd8501ec17c590a0c6f5be92e121381667ca726b6 (diff)
downloadgem5-abe18be544014bee31d586bf8b26ab5b622b70b7.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into vm1.(none):/home/stever/bk/newmem-head --HG-- extra : convert_revision : 8b0fbb6b1ea38d01d048381f18fd95ab63c4c0f1
Diffstat (limited to 'src/arch/alpha')
-rw-r--r--src/arch/alpha/isa_traits.hh5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index 72e38ae3e..4f439b8df 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -42,7 +42,6 @@ class StaticInstPtr;
namespace AlphaISA
{
-
using namespace LittleEndianGuest;
// These enumerate all the registers for dependence tracking.
@@ -60,12 +59,14 @@ namespace AlphaISA
StaticInstPtr decodeInst(ExtMachInst);
+ // Alpha Does NOT have a delay slot
+ #define ISA_HAS_DELAY_SLOT 0
+
const Addr PageShift = 13;
const Addr PageBytes = ULL(1) << PageShift;
const Addr PageMask = ~(PageBytes - 1);
const Addr PageOffset = PageBytes - 1;
-
#if FULL_SYSTEM
////////////////////////////////////////////////////////////////////////