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authorAndreas Sandberg <Andreas.Sandberg@ARM.com>2015-05-05 03:22:31 -0400
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>2015-05-05 03:22:31 -0400
commit1da634ace00dbae3165228b36655a62538c7c88d (patch)
tree3fbbc56c8ca5f2287caa16b8345990f4730e06ab /src/arch/alpha
parent23b9792681d4cd794b0ad74138160a37b8bdac8f (diff)
downloadgem5-1da634ace00dbae3165228b36655a62538c7c88d.tar.xz
mem, alpha: Move Alpha-specific request flags
Move Alpha-specific memory request flags to an architecture-specific header and map them to the architecture specific flag bit range.
Diffstat (limited to 'src/arch/alpha')
-rw-r--r--src/arch/alpha/faults.cc2
-rw-r--r--src/arch/alpha/isa/pal.isa4
-rw-r--r--src/arch/alpha/tlb.cc4
-rw-r--r--src/arch/alpha/types.hh16
4 files changed, 21 insertions, 5 deletions
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 2928f8d65..8bb781c13 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -147,7 +147,7 @@ DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
// on VPTE loads (instead of locking the registers until IPR_VA is
// read, like the EV5). The EV6 approach is cleaner and seems to
// work with EV5 PAL code, but not the other way around.
- if (reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
+ if (reqFlags.noneSet(AlphaRequestFlags::VPTE | Request::PREFETCH)) {
// set VA register with faulting address
tc->setMiscRegNoEffect(IPR_VA, vaddr);
diff --git a/src/arch/alpha/isa/pal.isa b/src/arch/alpha/isa/pal.isa
index 53e0d6193..3913fa82d 100644
--- a/src/arch/alpha/isa/pal.isa
+++ b/src/arch/alpha/isa/pal.isa
@@ -171,8 +171,8 @@ output decoder {{
{
memAccessFlags.clear();
if (HW_LDST_PHYS) memAccessFlags.set(Request::PHYSICAL);
- if (HW_LDST_ALT) memAccessFlags.set(Request::ALTMODE);
- if (HW_LDST_VPTE) memAccessFlags.set(Request::VPTE);
+ if (HW_LDST_ALT) memAccessFlags.set(AlphaRequestFlags::ALTMODE);
+ if (HW_LDST_VPTE) memAccessFlags.set(AlphaRequestFlags::VPTE);
if (HW_LDST_LOCK) memAccessFlags.set(Request::LLSC);
}
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 44326df40..bcf61f3bf 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -466,7 +466,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
}
if (PcPAL(req->getPC())) {
- mode = (req->getFlags() & Request::ALTMODE) ?
+ mode = (req->getFlags() & AlphaRequestFlags::ALTMODE) ?
(mode_type)ALT_MODE_AM(
tc->readMiscRegNoEffect(IPR_ALT_MODE))
: mode_kernel;
@@ -523,7 +523,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
if (write) { write_misses++; } else { read_misses++; }
uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
MM_STAT_DTB_MISS_MASK;
- return (req->getFlags() & Request::VPTE) ?
+ return (req->getFlags() & AlphaRequestFlags::VPTE) ?
(Fault)(std::make_shared<PDtbMissFault>(req->getVaddr(),
req->getFlags(),
flags)) :
diff --git a/src/arch/alpha/types.hh b/src/arch/alpha/types.hh
index b1411d46e..aaa0f0b2a 100644
--- a/src/arch/alpha/types.hh
+++ b/src/arch/alpha/types.hh
@@ -51,6 +51,22 @@ enum annotes
ITOUCH_ANNOTE = 0xffffffff
};
+/**
+ * Alpha-specific memory request flags
+ *
+ * These flags map to the architecture-specific lower 8 bits of the
+ * flags field in Request.
+ */
+struct AlphaRequestFlags
+{
+ typedef uint8_t ArchFlagsType;
+
+ /** The request is an ALPHA VPTE pal access (hw_ld). */
+ static const ArchFlagsType VPTE = 0x01;
+ /** Use the alternate mode bits in ALPHA. */
+ static const ArchFlagsType ALTMODE = 0x02;
+};
+
} // namespace AlphaISA
#endif // __ARCH_ALPHA_TYPES_HH__