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authorGabe Black <gblack@eecs.umich.edu>2007-07-31 17:34:08 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-07-31 17:34:08 -0700
commit4bdabe1254a8ad9bb960f57eb35cec919b370de8 (patch)
tree318b34065ed9eb3f30852fee11eb398a92134652 /src/arch/alpha
parent55ade789d34e541cc538c7c5a4f286a313cfd8ba (diff)
downloadgem5-4bdabe1254a8ad9bb960f57eb35cec919b370de8.tar.xz
Add a flag to indicate an instruction triggers a syscall in SE mode.
--HG-- extra : convert_revision : 1d0b3afdd8254f5b2fb4bbff1fa4a0536f78bb06
Diffstat (limited to 'src/arch/alpha')
-rw-r--r--src/arch/alpha/isa/decoder.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index af1a91a62..2177e8c4f 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -714,7 +714,7 @@ decode OPCODE default Unknown::unknown() {
}}, IsNonSpeculative);
0x83: callsys({{
xc->syscall(R0);
- }}, IsSerializeAfter, IsNonSpeculative);
+ }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
// Read uniq reg into ABI return value register (r0)
0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
// Write uniq reg with value from ABI arg register (r16)